IPUV3 Spec

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IPUV3 Spec

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ogj
Contributor III

Is there a separate document (besides the RM) that covers the IPU? I saw the following in a post:

ogj_0-1604438410728.png

Sorry about the size. I like to understand what I'm doing when I write code for hardware. The documentation for the IPU is really lacking. Recently I am trying to understand data mapping in the DC module. I understand that the IDMAC can format a pixel coming from system memory from just about any format and convert it into the internal format of RGBA (8:8:8:8). Then in the DC it is re-formatted to meet the needs of the LCD. My understanding is that going into the DC, the pixel data is 24-bits wide, I'm assuming left justified within each byte/color for formats not using all bits. The DC uses the MD_MASK and MD_OFFSET values to some how map the internal format into the format needed by the LCD. What I don't understand is how the values for mask and offset are determined. I will be using the RGB888 format going into the LCD. In the SDK, it gives the value for offset[0] as 23, offset[1] as 15 and offset [2] as 7. What do these numbers mean? I can't find any way that they are used as data shift values, to position the data. How do I come up with them? That's why I was wondering if there is another document (or code with more comments) that explains it.

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Yuri
NXP TechSupport
NXP TechSupport

@ogj 
Hello,

   Hope, the following helps:

https://community.nxp.com/t5/i-MX-Processors/Parallel-RGB-Displays/m-p/312589

 

 

Regards,
Yuri.

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ogj
Contributor III

I will assume that there is no public spec on the ipu and one must keep asking questions to better understand it. A few more questions. 

I am using a parallel 800 x 480 panel with 24-bit color, combining two full frame buffers. 

  1. I need to combine 2 full frame buffers coming from system memory – a background buffer and a foreground buffer. Where is the best place to combine them? I was planning on doing it in the DP, but judging from the DP_FG_POS_SYNC register and the write-up in the  SDK Firmware Guide, the DP can only combine a full and a partial buffer. Does this mean that the DP cannot combine two full buffers? If so, where is the best place to combine them?
  2. I’ve previously used the Vybrid processor. With that chip an “invisible” color could be created, and whenever that color was read from the fg buffer, it wasn’t written to the combined buffer. For example, on startup, the fg buffer was filled using that color and therefore was invisible when the buffers were combined. Bitmap images were then written to the fg in regular colors making them visible. It appears this capability also exists in the IPU. What is the best way to implement it? Can an “invisible” color be created, or is it all done using the alpha channel? What is the best way to implement?
  3. In the SDK ipu ipu_dc_write_channel_config function, one of the things that is written is the DC_WR_CH_CONF_5 register. The field  PROG_DISP_ID_5 is set to 2. What does this value mean? I thought the IPU only has di0 (which I’ll be using) and di1.
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Yuri
NXP TechSupport
NXP TechSupport

@ogj 
Hello,

  It would be better to create separate thread for the combine issue.

Regards,
Yuri

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