IPU DI LCD HDMI LVDS

[乐乐季]

hello everyone!

i'm use the imx6q. and patch the "Patch to Support BT656 and BT1120 Output For i.MX6 BSP", I want to use the DISP_DAT0-DISP_DAT15 for BT1120 YUYV16 data.

I have some questions for you!

1. I find the "LVDS0 source is IPU1 DI0 por" and "HDMI source is IPU1 DI0 port" at the IOMUXC_GPR3,but I not find DISP_DAT source is which one IPU and DI ?

2. the patch set  IPU_PIX_FMT_UYVY 16bit width for BT1120 at the ipu_disp.c. i don't Understand why this set. please tell me! and I want send the BT1120 YUYV16 data, Whether need add code for BT1120 YUYV16 data?

3.I set bootargs "video=mxcfb0:dev=bt656,BT1120-1080I60,if=BT1120,fbpix=YUYV16",the fbpix whether can be set as YUYV16?

My English is not good, please do not mind.

Thanks!

[qiang_li-mpu_se · Accepted solution]

For 1, the IPU1 DI0 display data pins are "IPU1_DISP0_DAT_xxx", and IPU1 DI1 display data pins are "IPU1_DISP1_DAT_xxx".

For 2, you can apply the patch "https://community.freescale.com/docs/DOC-100657", it was verified with UYVY16 1080i50 output on LCD interface, it should also work for 1080P.

For 3, you can add the followed video mode into mxc_lcdif.c, and video mode parameters in kernel command lines: "video=mxcfb0:dev=lcd,LCD-1080P50,if=UYVY16,fbpix=BGR32" or "video=mxcfb0:dev=lcd,LCD-1080P60,if=UYVY16,fbpix=BGR32".

{

/* 1920x1080p @ 60 Hz , pixel clk @ 148.5MHz */

"LCD-1080P60", 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,

FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

FB_VMODE_NONINTERLACED,

0,},

{

/* 1920x1080p @ 50 Hz , pixel clk @ 148.5MHz */

"LCD-1080P50", 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,

FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

FB_VMODE_NONINTERLACED,

0,},

[qiang_li-mpu_se]

1.Before I did not hit the patch to
my kernel, I use the "CLAA-WVGA" mode,I can measured clock pin have
signal ,but if I patch the "L3.0.35_4.1.0_GA_HDMI_Interlaced_Mode_Patch.zip"
to my kernel, I can measured data pin 、vsync
and hsync  have signal.but the clock pin don't have signal.How can I
solve?

[Qiang] You need check yout hardware if the correct "MX6Q_PAD_DI0_DISP_CLK" PIN had been measured?

2.I read your patch notes, It is the
support the interlace fo hdmi and lcd, I want the lcd  output 1080p,so I
think I don't need this patch,Because the kernel support the 1080p,I only add
the "/* 1920x1080p @ 50 Hz , pixel clk @
148.5MHz */" to my mxc_lcdif.c ,Is that
right?

[Qiang] No, you need apply that patch, because it added the UYVY16 output support.

[乐乐季]

HI Qiang,I'm sorry to change my problem:

1.Whether or not I have patched my kernel, if I set pixclock as 6734 for 148.5MHZ, the clock pin no signal,but if I set  pixclock as 13468 for 74.5MHz,the clock pin have signal. How can I solve?

2.You set the "if=UYVY16" at the bootargs,can I set the "if=YUYV16"?

3.if I set the "fbpix=BGR32", the "bits_per_pixel" is 32. I use the DISP_DAT0----DISP_DAT15 for data line,so I want the bits_per_pixel is 16. I changed the parameters as "video=mxcfb1:dev=lcd,LCD-1080P60,if=YUYV16", Is that right?

Thank you!

[qiang_li-mpu_se]

1. It should be the hardware board related, maybe you can adjust the PAD_CTRL setting for the pixel clock pin, register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK.
#define  MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  \

  (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))

2. All of UYVY16, YUYV16, YVYU16, VYUY16 can be supported.

3. The fbpix is the frame buffer data format, it is not related to your 16bits hardware interface(DISP_DAT0----DISP_DAT15). Of cource you can also set fbpix=RGB565 for 16bpp frame buffer, but the video quality will be poor than 32bpp/24bpp when it was converted to YUYV format.

[乐乐季]

Hi Qiang:

1.I register "MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK" at board-mx6q_sabrelite.c, and lcdif_data's ipu_id =0 disp_id =0.but the clock pin not have signal.

2. I change the "MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK " to "MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK ", and lcdif_data's ipu_id =1 disp_id =0.The situation is the same.

Whether the clock cannot be reached 148.5M?

[qiang_li-mpu_se]

I mean you need tune setting in register IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, it is electric related to the PIN.

For example enable pull up, increase drive stregth, set to Fast Slew Rate, MAXIMUM Speed Field ...

You can discuss it with your hardware engineer, I think they can understand it.

[乐乐季]

HI Qiang：

Thank you for your reply！

Your answer is very good , I reset the IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK, the clock pin have the 148.5MHZ, but the signal have a little wobble.and The amplitude is not big.

I set the Register is 0xB0F1:

bit 0 : 1 ----- FAST Slew Rate

bit 5-3: 110 ---- 40_OHM

bit 7-6: 11 ----MAXIMUM

bit 12: 1 ----Pull/Keeper Enabled

bit 13:1 ----Pull Enabled

bit 15-14:10 ----100K_OHM_PU.

other bit set 0.

I have the wrong place please set the register ?

[qiang_li-mpu_se]

The IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK register setting was defined in file "linux-3.0.35\arch\arm\plat-mxc\include\mach\iomux-mx6q.h"

#define  MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  \

  (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))

It was used in file "linux-3.0.35\arch\arm\mach-mx6\board-mx6q_sabresd.h".

[乐乐季]

Thank you answer me these questions! You really very much good!