Hi @HenryHsu
Here is my previous test on i.MX95 EVK, please check your dts with below modifications.
dts modification:
Zhiming_Liu_2-1785995739657.png
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index ab7bd4fdaadf..5eb3011f0894 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -380,7 +380,7 @@ &flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <®_can1_stby>;
- status = "disabled";
+ status = "okay";
};
&flexcan2 {
@@ -623,23 +623,23 @@ spidev0: spi@0 {
};
};
-&micfil {
- #sound-dai-cells = <0>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_pdm>;
- pinctrl-1 = <&pinctrl_pdm_sleep>;
- assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
- <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
- <&scmi_clk IMX95_CLK_AUDIOPLL1>,
- <&scmi_clk IMX95_CLK_AUDIOPLL2>,
- <&scmi_clk IMX95_CLK_PDM>;
- assigned-clock-parents = <0>, <0>, <0>, <0>,
- <&scmi_clk IMX95_CLK_AUDIOPLL1>;
- assigned-clock-rates = <3932160000>,
- <3612672000>, <393216000>,
- <361267200>, <49152000>;
- status = "okay";
-};
+// &micfil {
+// #sound-dai-cells = <0>;
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&pinctrl_pdm>;
+// pinctrl-1 = <&pinctrl_pdm_sleep>;
+// assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+// <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+// <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+// <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+// <&scmi_clk IMX95_CLK_PDM>;
+// assigned-clock-parents = <0>, <0>, <0>, <0>,
+// <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+// assigned-clock-rates = <3932160000>,
+// <3612672000>, <393216000>,
+// <361267200>, <49152000>;
+// status = "okay";
+// };
&mu7 {
status = "okay";
@@ -960,19 +960,19 @@ IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
>;
};
- pinctrl_pdm: pdmgrp {
- fsl,pins = <
- IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
- IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e
- >;
- };
+ // pinctrl_pdm: pdmgrp {
+ // fsl,pins = <
+ // IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
+ // IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e
+ // >;
+ // };
- pinctrl_pdm_sleep: pdmsleepgrp {
- fsl,pins = <
- IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x51e
- IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x51e
- >;
- };
+ // pinctrl_pdm_sleep: pdmsleepgrp {
+ // fsl,pins = <
+ // IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x51e
+ // IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x51e
+ // >;
+ // };
pinctrl_ptn5110: ptn5110grp {
fsl,pins = <
system manager modification:
diff --git a/configs/mx95evk.cfg b/configs/mx95evk.cfg
index 9250d02..6722097 100755
--- a/configs/mx95evk.cfg
+++ b/configs/mx95evk.cfg
@@ -389,7 +389,7 @@ SYS ALL
# Resources
M7P OWNER # CPUs must be first
-CAN_FD1 OWNER
+// CAN_FD1 OWNER
FSB READONLY
IRQSTEER_M7 OWNER
LPIT1 OWNER
@@ -612,6 +612,7 @@ CAMERA5 OWNER
CAMERA6 OWNER
CAMERA7 OWNER
CAMERA8 OWNER
+CAN_FD1 OWNER
CAN_FD2 OWNER
CAN_FD3 OWNER
CAN_FD4 OWNER
Result:
Zhiming_Liu_3-1785995783165.png