IMX93x : Can MIPI-CSI2 generate an interrupt triggered by an FS/FE packet?

[takayuki_ishii]

Hello community,

I hope to detect FS and FE packet receive timing on MIPI-CSI2.

Can an interrupt be triggered by an FS/FE packet in MIPI-CSI2 of IMX93?

I could not find it in the interrupt flag registers described in the reference manual rev2.0.

By the way, main interrupt status. (INT_ST_MAIN), there are 10 valid interrupt flags

for sub modules of MIPI-CSI2.

1. status_int_ipi_fatal[18]
2. status_int_phy[16]
3. status_int_ecc_corrected[7]
4. status_int_data_id[6]
5. status_int_pld_crc_fatal[5]
6. status_int_crc_frame_fatal[4]
7. status_int_seq_frame_fatal[3]
8. status_int_bndry_frame_fatal[2]
9. status_int_pkt_fata[1]
10. status_int_phy_fatal[0]

But only 4 of the 10 submodule registers are described in register map of Reference Manual.

1. 54.5.1.31 Fatal Interruption Caused by PHY (INT_ST_PHY_FATAL)
2. 54.5.1.34 Fatal Interruption Caused During Packet Construction (INT_ST_PKT_FATAL)
3. 54.5.1.37 Interruption Caused by PHY (INT_ST_PHY)
4. 54.5.1.40 Fatal Interruption Caused by IPI Interface (INT_ST_IPI_FATAL)

Are there any interrupts triggered by FS/FE in the remaining 6 interrupt factors

that do not have register descriptions?

Best regards,

Ishii.

[Bio_TICFSL]

Hello,

"With Line Interrupt Ratio" to 0x1. this setting, the LINE_END interrupt will be raised each time the Line End packet is detected on a specific MIPI CSI2 lane.

Regards

[takayuki_ishii]

Hello @Bio_TICFSL 

Thank you for your answerd..

And sorry my late reply.

I read your reply and search bits to set Line interrupt Ratio and LINE_END interrupt bit.

But I could not find those register bits.

1) In which register is "With Line Interrupt Ratio" located?

2) Where is the LINE_END interrupt?

LINE_RCVD_EN bit in 57.7.6 Channel Interrupt Enable (CHNL_IER) is correct?

I hope to know each interrupt of Frame Start(FS) and Frame End(FE) packet received timing.

If it set "Line Interrupt Ratio" = 1, LINE_END interrupt generate each Frame Start timing?

Best regards,

Ishii.

[Bio_TICFSL]

Hello,

From i.MX93 MIPI CSI RM, I haven't seen such interrupt that could indicates frame start or frame end MIPI CSI receives. Let me check with R&D if there is a way to get it. Will reply later.

regards

[Bio_TICFSL · Accepted solution]

Hello,

I checked with design about whether i.MX93 MIPI CSI has such FS/FE interrupt, unfortunately, there is no MIPI CSI interrupt about it. He mentioned there is an interrupt in ISI named as below that could do similar function:

It means whether the frame is stored successfully into memory. Although it is different with when MIPI CSI receive frame start/end packet, they could take a reference. 

Regards

[takayuki_ishii]

Hello @Bio_TICFSL 

Thank you for your reply.

I understand that MIPI-CSI module has no interrupt status signal.

But it is replaced by the ISI status signal, which does not exactly match.

Best regards,

Ishii.