IMX93 custom board ethernet dts changes

[vijay1251]

we are using imx93 where the 2 ethernet port lines are connected to  2 DP83867ERGZT 
give the proper dts changes for custom board , where reset pin we are using for gpio2_io09 and gpio2_io10 

#imx93

#DP83867ERGZT

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

First step is to confirm that your pin group matches EVK/FRDM so you can copy their pin group and pad configuration, if you are using RGMII most of the group will be reused.

Another important key is to know your MDIO topology, EVK/FRDM uses two MDIO buses to manage one PHY, if you used one bus to manage both, you will need to change DTS,

For module and PHY DTS, I can suggest this:

&eqos {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_eqos>;
	pinctrl-1 = <&pinctrl_eqos_sleep>;
	phy-mode = "rgmii-id";
// Depends on your PHY address
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

// Depends on your PHY address
		ethphy1: ethernet-phy@1 {
			reg = <1>;
                        eee-broken-1000t;
			reset-gpios = <&gpio 2 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
		};
	};
};

&fec {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec>;
	pinctrl-1 = <&pinctrl_fec_sleep>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy2>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy2: ethernet-phy@2 {
                        compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
			eee-broken-1000t;
			reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
		};
	};
};

Regards

[vijay1251 · Accepted solution]

hi joseph,

The below dts node changes is working fine in custom.
 

&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_eqos>;
status = "okay";

mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;

ethphy_eqos: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
interrupt-parent = <&gpi:wqo3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};

&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_fec>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;

ethphy_fec: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};

#imx93 #dp38367 

[vijay1251]

Hi jikehal
Thanks for your response.
I expect some reference node details.I didn't expect this kind of reply. May be you can say things in polite way.