/*
* DPU clock definition
*
* Resource Clock Description
* SC_R_DC_0 SC_PM_CLK_MISC0 Display 0 clock
* SC_R_DC_0 SC_PM_CLK_MISC1 Display 1 clock
* SC_R_DC_0_PLL_0 SC_PM_CLK_PLL User programmable PLL clock
* SC_R_DC_0_PLL_1 SC_PM_CLK_PLL User programmable PLL clock
* SC_R_DC_0_VIDEO0 SC_PM_CLK_MISC Bypass 0 clock
* SC_R_DC_0_VIDEO1 SC_PM_CLK_MISC Bypass 1 clock
*/
err = sc_pm_set_resource_power_mode(ipc, DC_RSRC, SC_PM_PW_MODE_ON);
if (SC_ERR_NONE != err)
{
assert(false);
}
err = sc_pm_set_resource_power_mode(ipc, DC_PLL_RSRC, SC_PM_PW_MODE_ON);
if (SC_ERR_NONE != err)
{
assert(false);
}
/* DPU PLL0. */
dpuPllClkFreq_Hz = APP_PIXEL_CLOCK_HZ * 8;
err = sc_pm_set_clock_rate(ipc, DC_PLL_RSRC, SC_PM_CLK_PLL, &dpuPllClkFreq_Hz);
if (SC_ERR_NONE != err)
{
assert(false);
}
err = sc_pm_clock_enable(ipc, DC_PLL_RSRC, SC_PM_CLK_PLL, true, false);
if (SC_ERR_NONE != err)
{
assert(false);
}
Failure to debug will result in the assert(false) function
(1) The M40 of IMX8QM does not support DPU operation.
(2) Is DPU configuration required in SCFW
