IMX8MQ Camera mipi Question

[qingyang601]

hi ,

I'm developing camera mipi driver on IMX8MQ-evk board, my camera output data is RAW-10bit.

When I refer to ov5640 driver code , I encountered below issues.

1. in 'drivers/media/platform//mxc/capture/mx6s_capture.c' , there are some registers as below, but I can't find any clue about below registers in Reference Manual .(from review code, I know these register's base address is 0x0x30A90000)

#define CSI_CSICR1 0x0
#define CSI_CSICR2 0x4
#define CSI_CSICR3 0x8
#define CSI_STATFIFO 0xC
#define CSI_CSIRXFIFO 0x10
#define CSI_CSIRXCNT 0x14
#define CSI_CSISR 0x18

#define CSI_CSIDBG 0x1C
#define CSI_CSIDMASA_STATFIFO 0x20
#define CSI_CSIDMATS_STATFIFO 0x24
#define CSI_CSIDMASA_FB1 0x28
#define CSI_CSIDMASA_FB2 0x2C
#define CSI_CSIFBUF_PARA 0x30
#define CSI_CSIIMAG_PARA 0x34

#define CSI_CSICR18 0x48
#define CSI_CSICR19 0x4c

2. same question as upon , can't find out any introducation about below registers(0x180~0x198) in Reference Manual.(base address is 0x30A70000)

in "driver/media/platform/imx8/mxc-mipi-csi2_yav.c" , 

printk("MIPI CSI2 HC IGNORE_VC 0x180 = 0x%x\n",          readl(csi2dev->base_regs + 0x180));
printk("MIPI CSI2 HC VID_VC 0x184 = 0x%x\n",                   readl(csi2dev->base_regs + 0x184));
printk("MIPI CSI2 HC FIFO_SEND_LEVEL 0x188 = 0x%x\n", readl(csi2dev->base_regs + 0x188));
printk("MIPI CSI2 HC VID_VSYNC 0x18C = 0x%x\n", r         eadl(csi2dev->base_regs + 0x18C));
printk("MIPI CSI2 HC VID_SYNC_FP 0x190 = 0x%x\n",       readl(csi2dev->base_regs + 0x190));
printk("MIPI CSI2 HC VID_HSYNC 0x194 = 0x%x\n",          readl(csi2dev->base_regs + 0x194));
printk("MIPI CSI2 HC VID_HSYNC_BP 0x198 = 0x%x\n",    readl(csi2dev->base_regs + 0x198));

3. in Reference Manual, mentions some "Data Type" as below,

" 13.6.3.6.4  RAW10 (Data Type = 0x2B) "

how do I set value 0x2B to Data Type?

My Reference Manual version is :

name : i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual

Document Number: IMX8MDQLQRM

Rev. 0, 01/2018

[RutvijTrivedi207]

I’ve seen this exact behavior on multiple i.MX8MQ MIPI-CSI bring-ups — the driver usually looks fine, but the failure happens due to subtle issues in the CSI-2 lane mapping, data type, or the clock tree when the display/HDMI side comes up.

On i.MX8MQ, the CSI-2 receiver is extremely strict about:

• Correct data-type matching (RAW10 vs RAW8 vs YUV422)

• Correct lane polarity + mapping

• Stable sensor clock once the DISP/HDMI PLLs switch

• Proper pinctrl (many boards accidentally leave a data lane in GPIO mode)

If any one of these mismatches happen, the CSIS block stays “streaming” but silently drops all packets — looks very similar to what you described.

For reference, here are a few upstream MIPI/CSI camera drivers we worked on that show the exact DT patterns and CSI setup sequences that typically solve this on i.MX8-class SoCs:

• Example of a MIPI sensor driver in Linux-next
  https://web.git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=fa9e6df636fb8b3b2...

Another sensor bring-up in Zephyr (useful for comparing the MIPI/clock sequences)
https://github.com/zephyrproject-rtos/zephyr/commit/c784481ca039ccd606a192ee07bc83f6b0117e59

Media pipeline update example (CSI routing + format negotiation)
https://web.git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=9d382f6a997891631...

And if you're designing the full camera pipeline (sensor → MIPI → CSI-2 → ISP/display), this deep-dive might help:

https://siliconsignals.io/blog/v4l2-camera-stack-step-by-step-guide-for-custom-devices/
https://www.kernel.org/doc/html/v4.9/media/kapi/v4l2-intro.html

[jameskim]

Hi,

I'm seeing at exact same issue. Have anyone resolved this issue receiving 10 bit?

Regards,

James

[lepol]

Hi Yang,

1. These registers do not match with any registers implemented on iMX8.
2. The registers are not supported on iMX8 yet.

3. There is a register Data type disable (offset 0x38) for input data type reformating but you can ignore it. If you set correctly camera and ISI register to target data type then it should work either.
If you have other questions, feel free to ask.

Good luck,

Lenka

[qingyang601]

Hi Lenka,

Thanks for your help.

Currently, I can receive one complete image, but the image isn't stable. after 1 minute, the image will be dislocation. The camera sensor's vendor  suggested that modify MIPI-CSI pixel clock, as you know, there are not useful information about MIPI CSI in RM. I found some documents on NXP website as below, but I'm still confused cause it's for iMX6. 

https://www.nxp.com/files-static/32bit/doc/app_note/AN5305.pdf

According this document, 

I try to modify 'IMX8MQ_CLK_CSI1_PHY_REF_DIV' to  <178560000>, but verify to linux system file that's not match.

My Question is , 

1. 'IMX8MQ_CLK_CSI1_PHY_REF_DIV'  is MIPI clock , right ?

2  'IMX8MQ_CLK_CSI1_CORE_DIV' and 'IMX8MQ_CLK_CSI1_ESC_DIV' , what’s purpose ?

3. How to modify  'IMX8MQ_CLK_CSI1_PHY_REF_DIV' value to exactly what's I want ?

my camera is 1280x800, 60fps, Gray 10bit. 2-lane

And I comments 'base addr switch' functionality, otherwise kernel will print "base address switching Change Err". I'm not sure this is necessary behavior.

Thanks.

Yang Qing

[lepol]

Hi Yang,

I would not recommend you to change MIPI PHY clock in the device tree. You wrote that your camera is 1280x800, 60fps, Gray 10bit. 2-lane, I suppose that this config is not supported in the BSP directly. You also wrote that after some time the image is dislocated. From my experiences this happens if camera registers are not set correctly for the given resolution, if the camera clock is not stable. Neverthless you don't need to use iMX6 documents/sources for iMX8 family mcu. Could you possibly provide the register settings in range of 0x3800 ~ 0x3815 and 0x3035 ~ 0x3037?
I also have problem to set 720p resolution at 60fps. I will try to contact the camera owner to ask for help with this type of configuration.

Kind regards,
Lenka

[qingyang601]

Hi Lenka,

Thanks for your reply. I have resolved this issue.  one more question puzzles me ,

I always think MIPI CSI driver should receive 1280000 bytes (1280*800*10bit / 8 ) per one frame, but actually it's 1024000 bytes(1280x800). I don't know the reason. According to RM(imx6) as below, for RAW10 data size should be (n * pixel * 5 / 4 ) bytes.

[wasim_nazir]

Hi qingyang601@hotmail.com‌,

Can you share some details on what changes you need to do to resolve these issue?

For me 4-bits are missing on every pixel. I have started a thread for my issue. Please have a look.

https://community.nxp.com/message/1195672 

Thanks in advance,

Wasim 

[kaartic_sn]

Hi qingyang601@hotmail.com‌,

Could you share some information about how you solved the issue? I ask this as we are facing a similar issue and it would nice to know a little more information about how you solved your issue. Was it a problem in the platform side or in the sensor side?

Thanks in advance,

Sivaraam

[igorpadykov]

Hi Yang

for 1. register descriptions one can look RM for imx6sll, as described in discussion on

iMX8M MIPI-CSI 4-lane configuration 

For other questions (not described in reference manual) may be recommended to

apply to nxp local marketing office. Note, there will be new reference manual revisions

with updated information.

Best regards
igor
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