Hi,
I am allowed to share some personal thought on this subject :
you can select version on the top right corner, try again
"https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8mp-evk-b..."
The solution proposed by @joanxie seems to be with 2 independent pipelines :
1. Basler camera --> MIPI0 --> ISP0
2. OV5640 camera --> MIPI1 --> ISI1
Meanwhile, I would guess that @malik_cisse expects to be able to access simultaneously different /dev/videoX and /dev/videoY for the same input camera :
a. IMX477 --> MIPIx ---> ISPx (bypass the demosiacing for having RAW bayer output on /dev/videoX)
|
+--> ISPy (YUV output on /dev/videoY)
b. IMX477 --> MIPIx ---> ISIx (RAW bayer output on /dev/videoX)
|
+--> ISPx (YUV output on /dev/videoY)
c. IMX477 --> MIPIx --> ISIx --> ISPx (YUV output on /dev/videoX)
|
+--> RAW bayer output on /dev/videoY
d. IMX477 --> MIPIx --> ISIx --> ISPy (YUV output on /dev/videoY)
|
+ --> RAW bayer output on /dev/videoX
However, I think that neither of above a, b, c, d is feasible.
not sure if it will answer your question, but in theory one CSI2 channel can output to ISI and ISP at the same time. It should look like this:
|------------------------> ISI0
CSI2 -------->| (no need any operation of register for this mux)
|-------------------------> ISP0
Moreover, I am not sure if the above theory of @dianapredescu (which is same to above case b) works since I haven't seen similar configuration in any reference dts until now.
And the following application note is only limited at single MIPI to dual ISIs, but no info about ISP : https://www.nxp.com/docs/en/application-note/AN13430.pdf
Best Regards,
K.