IMX8MP LPDDR SIZE change

[coindu]

     Dear community:

              I have some doubts about the LPDDR size change.   

              use DDR TOOLS to generator lpddr4_timing.c and modify the include/configs/xxxx.h PHYS_SDRAM ,PHYS_SDRAM_SIZE, and PHYS_SDRAM_2_SIZE  in uboot stage. And it is important to modify imx-atf,optee-os and imx-boot too.

             Now I want to change LPDDR4 from 6G to 3G.

             optee-os :core/arch/arm/plat-imx/conf.mk  set CFG_DDR_SIZE from 0x180000000 to 0x 0XC0000000

 ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
CFG_DDR_SIZE ?= 0x180000000ULL
CFG_UART_BASE ?= UART2_BASE
$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
$(call force,CFG_CORE_ARM64_PA_BITS,36)
endif

              imx-boot :iMX8MX/soc.mak   

else ifeq ($(SOC),iMX8MP)
PLAT = imx8mp
HDMI = no
SPL_LOAD_ADDR = 0x920000
SPL_FSPI_LOAD_ADDR = 0x920000
TEE_LOAD_ADDR = 0x56000000
ATF_LOAD_ADDR = 0x00970000
VAL_BOARD = val

               imx-atf: plat/imx/imx8m/imx8mp/platform.mk

BL32_BASE ?= 0x56000000
$(eval $(call add_define,BL32_BASE))

BL32_SIZE ?= 0x2000000
$(eval $(call add_define,BL32_SIZE))

             I donot understand that why the TEE_LOAD_ADDR and BL32_BASE is set to 0x56000000. If want to change 6G to 3G ,how to modify the two part?

[igorpadykov]

Hi Coin

TEE entry address is started from the top 32MB of available DDR memory, one can look at example in
i.MX8MQ EVK which also has 3GB memory. In general when DDR size was changed, one can directly
disable OPTEE in yocto configuration file, TEE binary won't be generated & be loaded into memory.

Best regards
igor

[coindu]

Thanks for your replying.

        I have seen the document about how to change DDR size on IMX8MQ or IMX8MM . If i want to change DDR size and enable optee ,  The optee address must be modify，otherwise the memory will be unstable.

        The address of IMX8MP makes me wonder, I need to know the correct address and change it.