[IMX8] CSI Fencing Timeout

[khaledbalbaa]

In the APIs MIPIDeinit and MIPIEnable I remarked that we are counting from 0 to 10,000,000 after  setting the register PHY_FENCE_CTRL waiting for the register PHY_FENCE_STATUS to be set to the same value as the CTRL register

As we know, this register is responsible for the virtual CSI channels and in our case we would like to not have any virtual channels, so we are setting the CTRL register to 0x0F and waiting for the status register to be also 0x0F, but we are waiting to the end of the timeout and the register still the same (0x00)

Questions:

1. Am I using the correct value to set the CSI with no virtual channel?

2. Why am I receiving a timeout?

3. Can the status register take this much time between the CTRL register write and the status register setting? Or this timeout could be reduced?

[khaledbalbaa]

Sorry forgot to mention it

We are working on IMX8DX processor

[khaledbalbaa]

@joanxie I am working with I.MX8 DX processor as mentioned

[joanxie]

sorry for missing this message, how about now?

[khaledbalbaa]

@joanxie 

Still having the same question actually

The register I am asking about is named STREAM_FENCING_CONTROL, offset 0x48 in CSI registers

[joanxie]

got the reply from the expert team:

"The stream_fencing is used to tell the MIPI CSI2 stop data transfer to pixel link.

For example, software can write "Fence VC0" to STREAM_FENCING_CONTROL register, then after MIPI CSI2 stops to transfer VC0 data to pixel link, the status "VC0 is fenced" can be read from STREAM_FENCING_STATUS register.

MIPI CSI2 reset can recover it.

"

[khaledbalbaa]

Hello @joanxie 

Thanks for the reply, but I think you have missed some of my question

My question was:

In the APIs MIPIDeinit and MIPIEnable I remarked that we are counting from 0 to 10,000,000 after  setting the register PHY_FENCE_CTRL waiting for the register PHY_FENCE_STATUS to be set to the same value as the CTRL register

As we know, this register is responsible for the virtual CSI channels and in our case we would like to not have any virtual channels, so we are setting the CTRL register to 0x0F and waiting for the status register to be also 0x0F, but we are waiting to the end of the timeout and the register still the same (0x00)

Questions:

1. Am I using the correct value to set the CSI with no virtual channel?

2. Why am I receiving a timeout?

3. Can the status register take this much time between the CTRL register write and the status register setting? Or this timeout could be reduced?

[joanxie]

I found another register named "Ignore Virtual Channel Register", the default is 0, which mean can accept all of VC, how about setting this to 1 since you don't want o use any VC

[joanxie]

what CTRL register do you mean? PHY_FENCE_CTRL?? I couldn't find this register from the reference manual, could you tell me how you decide the value of these registers?

[joanxie]

what processor are you talking about? imx8qm?