IMX7D eth1 no RX

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IMX7D eth1 no RX

749件の閲覧回数
vishnupratap_si
Contributor I

Hi,

we are using iMX7D sabre board design, but we have two micrel ethernet controller.  Currently we are facing issue when we are trying to do the communication we are not able to get any TX/RX for eth1.

ifconfig
eth0      Link encap:Ethernet  HWaddr FE:15:31:D8:6D:AC
          inet addr:192.168.1.3  Bcast:192.168.1.255  Mask:255.255.255.0
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

eth1      Link encap:Ethernet  HWaddr C6:15:56:FD:91:52
          inet addr:192.168.1.4  Bcast:192.168.1.255  Mask:255.255.255.0
          inet6 addr: fe80::c415:56ff:fefd:9152%lo/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:27 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:5139 (5.0 KiB)

for eth1 we are seeing few TX bytes, but not able to communicate.

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>;
/* pinctrl-assert-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; */  
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};

ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};

&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>;
 pinctrl-0 = <&pinctrl_enet2>; 
pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
/* pinctrl-assert-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; */
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
};

How to debug this issue,can some one please provide some input to debug this issue.

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599件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Vishnu

could it be misprint as fec1 and fec 2 have different polarities:
pinctrl-assert-gpios = ACTIVE_HIGH, ACTIVE_LOW.
One can test fec2 in uboot setting appropriate
#define CONFIG_FEC_ENET_DEV in include/configs/mx7dsabresd.h

Best regards
igor
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