IMX6ULL RTCs Year 2038 Compliant On A Hardware Level

[nwinston]

Hello,

On a hardware level (not software level as Yocto Linux seems to have fixed this: https://community.nxp.com/t5/i-MX-Processors/IMX8M-yocto-linux-NTP-bug-aka-Y2K38/m-p/1264476 ), is the IMX6ULL and it's RTCs (both the unsecured SNVS_HP and the secured/battery backed SNVS_LP / SRTC) 64-bit and thus Year 2038 compliant?

Looking at section 48.7.6 of the IMX6ULL reference manual shows the structure of SNVS_HP which looks to be 64-bit but it doesn't explicitly say if it's Y2K38 compliant or not.

Furthermore I cannot find any illustration nor mention of the SRTC, if it's 64-bit or not nor if it's Y2K38 or not either.

My concern scenario is the following: Say the IMX6ULL is powered down (Linux is not running) around Jan 19 2038, but the battery backed up SNVS_LP SRTC is running. Will that roll over/overflow or will it keep ticking? I know that the latest Yocto Linux + Network Time Protocol can correct this (once finished booting) but there's a window in pre-boot / booting where that potential roll over could be problematic.

Any help is appreciated, thanks.

,Nick

[b36401]

It is 64bit value divided by 2 32bit registers.
Please refer to chapter 48.6.2

[nwinston]

I looked also in the IMX6ULLSRM Security Ref Manual and found a register description for the SNVS LP SRTC (I suppose it was removed from the IMX6ULLRM for security reasons..?)

Anyways now there's a conflict as I find not only the SNVS LP SRTC but also the SNVS HP Unsecured RTC register description in the IMX6ULLSRM (Chap 7 Section 9). However the SRM shows that both the SRTC and HP uRTC are 48 bit real time counters, not 64 bit like shown in the IMX6ULLRM.

The SNVS LP monotonic counter register description matches between the RM and SRM atleast.

So verifying which is correct for the SNVS LP SRTC and SNVS HP uRTC? Is it the RM stating that they are 64 bits or is it the SRM with it stating that they are 48 bits?

Thanks,

Nick

[b36401]

About SRTC, you can find more detailed information in 6ULL SRM.

In SRM, we can find the SNVS_LP Counter registers LPSRTCLR and LPSRTCMR.
The LPSRTCLR has 32 bits, the LPSRTCMR has 15 bits, so the SNVS_LP SRTC has 47bits, which can reach 2106. Feb. 27th if we set the base as 1970-1-1. It won't have Y2K38 issue.

In addition, SRTC is a non-rollover counter which means that the SRTC does not roll over when it reaches the maximum value of all ones.
Instead, a time rollover indication is generated to the SNVS_LP tamper monitor which generates a security violation and an interrupt.

[b36401]

I asked the Team. Please wait a bit.