Hi,
we are using an isl79987 chip for capturing up to 4 analog camera.
I've applied the patch from nxp wich allow 4 channel capturing and displaying on a hdmi screen on a 4.19 kernel (using nxp bsp)
Test are done using the nxp test application mxc_v4l2_tvin.out
below the command launch:
./mxc_v4l2_tvin.out -ol 0 -ot 0 -ow 960 -oh 540 -d 1 -x 0 -m 1 -g2d &
./mxc_v4l2_tvin.out -ol 960 -ot 0 -ow 960 -oh 540 -d 1 -x 1 -m 1 -g2d &
./mxc_v4l2_tvin.out -ol 0 -ot 540 -ow 960 -oh 540 -d 1 -x 2 -m 1 -g2d &
./mxc_v4l2_tvin.out -ol 960 -ot 540 -ow 960 -oh 540 -d 1 -x 3 -m 1 -g2d &
Everything works now, and i'm trying to understand the impact on cpu and ram.
For this i use htop (for cpu side) and mmdc tools for memory side.
I see that CPU load is not so much, which can be explained by the fact that most of the work is done by the IPU.
The question is more on the mmdc result:
0 channel:
ipu1: utilization: 27%
overall bus load: 10%
ipu2: utilization: 0%
overall bus load: 0%
1 channel capture and display:
ipu1: utilization: 42%
overall bus load: 15%
ipu2: utilization: 0%
overall bus load: 0%
2 channel capture and display:
ipu1: utilization: 35%
overall bus load: 19%
ipu2: utilization: 4%
overall bus load: 23%
3 channel capture and display:
ipu1: utilization: 28%
overall bus load: 24%
ipu2: utilization: 4%
overall bus load: 23%
4 channel capture and display:
ipu1: utilization: 26%
overall bus load: 27%
ipu2: utilization: 5%
overall bus load: 27%
I don't really understand why with only 2 channel, IPU2 load the ram bus.
And after, if we add channel3 and 4, IPU2 overall bus load seems to follow ipu1 overall bus load.
Moreover, does this mean that with 4 channel, memory bus load is 27% or 54%?
Would you have some explaination, or could you indicate where i can find some informations on how it is working?
Thans in advance.
Regards
Laurent
