IMX6 DDR Stress Test affected by ARM Core Clock Changes

[tomsaluzzo]

Using the IMX6D and running the DDR Stress Test and getting failures (one byte with incorrect data) when the ARM Core Clock set to 996MHz. Changing the ARM Core Clock to 792MHz results in DDR Stress Tests passing. How does changing the ARM Core Clock (PLL1) affect the DDR Stress Test? The DDR clock is set by PLL2.

[igorpadykov]

Hi Tom

some parts, like MCIMX6D6AVT08AC work only up 852MHz.

One can check if VDD_ARM adjusted for operation up to 996MHz.

Another reason may be noise and ripples due to increased power consumption

on higher frequencies, this can be checked with oscilloscope and Chapter 2,

Chapter 8 Avoiding Board Bring-up Problems

i.MX6 System Development User’s Guide (rev.1, 6/2013)

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards

igor

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[tomsaluzzo]

We have verified the voltage noise and ripple is good.

What else can be the cause of failures at the higher ARM Core Clock?

Please confirm that the ARM Core Clock (ARM_CLK_ROOT/PLL1) has no direct affect on the DRAM clock or DRAM operation. In other words, do changes to the ARM_CLK_ROOT result in anything directly changing in the DRAM interface/timing?

[igorpadykov · Accepted solution]

yes, ARM Core Clock (ARM_CLK_ROOT/PLL1) has no direct affect on the DRAM clock or DRAM operation.

You can try to run this test on Freescale reference board.