Dear NXP Support Team,
I am making eDMA memory to memory transfer that I want to allow or not from writing in a specific memory address by using the XRDC2.
The issue is that I can't manage to make the access policy work right.
Here is how I assign a Domain ID to the eDMA Bus Master :
xrdc2_master_domain_assignment_t assignment;
XRDC2_GetDefaultMasterDomainAssignment(&assignment);
/* Defining privileges to the EDMA */
assignment.lock = false;
assignment.privilegeAttr = kXRDC2_ForcePrivilege;
assignment.secureAttr = kXRDC2_ForceNonSecure;
assignment.domainId = 3;
XRDC2_SetMasterDomainAssignment(DEMO_XRDC2, kXRDC2_Master_M7_EDMA, 0, &assignment);
XRDC2_SetMasterDomainAssignment(DEMO_XRDC2, kXRDC2_Master_M4_EDMA, 0, &assignment);
Here is how I assign the access rights to the memory that I want to manage with the XRDC :
xrdc2_mem_access_config_t memAccessConfig;
XRDC2_GetMemAccessDefaultConfig(&memAccessConfig);
memAccessConfig.startAddr = DEMO_XRDC2_MEM_START_ADDR;
memAccessConfig.endAddr = DEMO_XRDC2_MEM_END_ADDR;
memAccessConfig.policy[3] = kXRDC2_AccessPolicyAlt6;
But this configuration blocks the EDMA transfer from happening. Normally the transfer should happen as eDMA is assigned to the Domain ID 3 that has the NonSecurePriv attributes and as I am using the kXRDC2_AccessPolicyAlt6 policy (which gives NonSecurePriv transfers read and write rights) over the memory I want to manage with the XRDC2.
I only manage to block or allow that eDMA transfer when assigning the eDMA to the Domain ID 0 (which is the default one) and when I use the kXRDC2_AccessPolicyAll and kXRDC2_AccessPolicyNone access policy. I don't understand actually why the other access policies does not work as intended when using the Domain ID 0. For example when using kXRDC2_AccessPolicyAlt3 the transfer is happening but it should not.
I feel like I am not not assigning the eDMA Bus Master to the Domains correctly. That is why the behaviors of the eDMA transfers are not working like I want.
In case you need more details or bites of my code feel free to reach out ! Thanks !
已解决! 转到解答。
Hi @mneroda ,
The match for M7 DMA is MATCH[14:0]= {CHANNEL_ID[4:0],HMASTER[3:0],XID[5:0]} , you may mask the XID part, and set up CHANNEL_ID and HMASTER according to your application. Please kindly refer to the following for details.
CHANNEL_ID: channel id from EDMA, indicates DMA channel index
• HMASTER: Master id from EDMA, indicates the master id of master that
programmed the DMA channel that is active
Have a great day,
Kan
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Hi @mneroda ,
Did you also set up assignment as below? Please kindly clarify.
assignment.mask = 0xFFFFFFFFUL;
assignment.match = 0UL;
Have a great day,
Kan
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Hi @Kan_Li ,
Thanks a lot for your answer.
Yes I've set up the assignment as you did and I managed to block the eDMA transfer with the XRDC as I wanted. I did another post that shows how I am making that assignment : https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/IMX-RT1170-EVKB-How-to-configure-XRDC2-domain-as....
However, I would like to know if it is possible to fine tune the MASK and MATCH field because by setting the fields as you show it seems like a hit is generated for all the eDMA transfers (I only want to block the DMA0 transfers). The previous link I have shared is a post about this topic.
Have a great day,
Mickaël
Hi @mneroda ,
The match for M7 DMA is MATCH[14:0]= {CHANNEL_ID[4:0],HMASTER[3:0],XID[5:0]} , you may mask the XID part, and set up CHANNEL_ID and HMASTER according to your application. Please kindly refer to the following for details.
CHANNEL_ID: channel id from EDMA, indicates DMA channel index
• HMASTER: Master id from EDMA, indicates the master id of master that
programmed the DMA channel that is active
Have a great day,
Kan
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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