IMX 8M DRAM_VREF Voltage

[AdrianMerrath]

Hello,

I have two questions refering to the DRAM_VREF voltage (Pin AA14) of the i.MX 8M.

1) What is the absolut maximum rating for this pin? In the datasheet it is assigned to the group "NVCC_DRAM" (table 85, IMX8MDQLQIEC). So can we assume -0.3 to 1.42 V (Table 5, IMX8MDQLQIEC) here?

2) In the latest Hardware Developer Guide (IMX8MDQLQHDG) it is recommended to leave this pin unconnected, because "The VREF signal for LPDDR4 is generated internally by the processor" (Table 3, Point 4). When the PMIC output is disconnected, there is no voltage output at this pin.
So I would like to know if it is just an option to use the internal supply or if an external supply is not used anyway, maybe because the pin is not connected inside the i.MX 8M? This would also mean that we don`t need any external capacitors and on top, a connected source, which had been switched of by Software, has no negative effect to the internal Regulator.

Best regards,
Adrian

[Yuri]

@AdrianMerrath 
Hello,

    Please look at my comments below.

1. Correct, NVCC_DRAM max rating specs are applied for DRAM_VREF.
2. Yes, the VREF pin can be left unconnected. Moreover, the DDR PHY
performs the VREF training as part of the calibration procedure.

Regards,
Yuri.

[AdrianMerrath]

Hi @Yuri ,

thanks for you reply.

Maybe you can give an advise refering point 2:
We are using an external voltage source for DRAM_VREF. We can switch it off by software, but this would be done later that the VREF Training. Is the internal voltage source used for the VREF Trianing anyway or could there be any problems when switch the external DRAM_VREF source off after the VREF Training?

Best regards,
Adrian

[Yuri]

@AdrianMerrath 
Hello,

   "DRAM_VREF was made by external regulator on older EVK/HDG.

I suppose that an internal setting of DRAM PHY allows to select internal/external source for DRAM_VREF and it is used for VREF training. So, an external voltage source of DRAM_VREF
should have no influence as long as the internal source from SoC is used by SW."

Regards,
Yuri.

[AdrianMerrath]

Hi @Yuri ,

with an internal setting of the DRAM PHY you mean the setting in the MX8M_LPDDR4_RPA document? Can you tell me which parameter chooses the VREF Source there? I couldn`t find it.

Best regards
Adrian

[Yuri]

@AdrianMerrath 
Hello,

   if an external VREF is not applied, internal one is used automatically.

Regards,
Yuri.