I do not understand how pinmux to gpio works in device tree

[JohnKlug]

I am using the i.mx6.  I am looking at the evaluation board software in Yocto.  I will eventually need to write my own gpio/pinmux code in device tree.  I have done this for other vendors' CPU's, but do not understand how this works with yours.  For our design we have created an MEX file using the tool, but gpio-ranges are not in the output.  Should the be?

For the evaluation board, we are using the following:

git submodule https://source.codeaurora.org/external/imx/linux-imx.gi with hash babac008e5cf168abca1a85bda2e8071ca27a5c0.  MACHINE=imx6ull14x14evk

I assume the device tree starts here:

imx6ull-14x14-evk.dts

In imx6ul.dtsi  I see the following code:

gpio1:  ...

gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;

...

gpio5:  ...

gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;

How does one find out what number to actually use to do this mapping.  In other words for <&iomuxc 0 23 10>,  I know that this means to match pincontroller pin offset 23 to gpio offset 0, for 10 pins.  But what in device tree mates with pin 0 in gpio1, and what mates with 23 in iomuxc?

Can this somehow be known from other parameters in the device tree?  Are there hardware restrictions built into the imx6 processor that are deciding what pinmux pin maps to which GPIO pin?

Also, looking at the kernel debug file system on the evaluation board, I see this in the gpio attribute:

gpiochip5: GPIOs 504-511, parent: spi/spi5.0, 74hc595, can sleep:
gpio-507 ( |regulator-can-3v3 ) out hi ACTIVE LOW

So gpiochip 5 has a range from 504 to 511.  How was this decided?  I don't see these values in the device tree mapping.

Is this referencing gpiochip5 (from the kernel debug) in the code below?  I see the count of pins is 12, which does not match 504-511.  But the GPIO #'s start at 0 and 10, which would give a range from 0-11.

gpio5: gpio@20ac000 {
compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
};

[joanxie]

since you use imx6ull, refer to the imx6ull.dtsi, I don't find gpio-range, anyway, if you need to know this, you can refer  to the document in the source code:

https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/gpio/gpi...

[JohnKlug]

imx6ull.dtsi includes imx6ul.dtsi.

If you would read imx6ul.dtsi, you would see it contains gpio-ranges.

imx6ul.dtsi line 467

This code does not come out of your tool.  So for the MCIMX6ULL-EVK, I would like to know the reasoning.

Here we have:

gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
					      <&iomuxc 16 33 16>;

I know this means map pinmux pins 23-32 onto gpio 0-9.  But why were these chosen?

Then we map pinmux pins 17-22 onto gpio 10-15.  Then 33-48 onto 16-31.  So the GPIO # are 0-31 specified here.  This is a total of 32 GPIO pins, put cotroller pins start at 17 and go to 48.  Why?

Also, why does the kernel debugger show gpiochip5 starting at gpio 504?

[osipovvo]

I've found answer for first part of your question, bcs tried to find the same answer. The second parameter from gpio-range is offset to specific iomux register (need to "x4" and tranlsate to hex). This also was answered here https://community.nxp.com/t5/i-MX-Processors/DTS-files-syntax-for-gpio-ranges-with-iomuxc/m-p/618092