I.MX8QM DDR configuration.

[arunkvnss]

Dear NXP expert,

I would like to take your attention to my small problem, Since i suspect the issue belongs to the DDR, It takes lots of my energy to identify the root cause. We have 2 board with I.MX8QM Soc. One board is successfully booting and we able to get root login and run our applications on the userspace. But the other board is showing up some sort of problems and i really suspect it because of the DDR configuration issue (May be Row and column access strobe values).  3 out of 10 the board is booting and stuck due to some kernel NULL pointer reference. and most of the time it stuck in the SPL. Hence i would like to chnage its DDR row and column access strobes to see any progress is coming up. I have 1.6GHz DCD file with me, But i dont know where i can edit the Column and Row access strobes values.

So could you please help me to resolve this issue. ?. I have listed my queries below.

1 ) Please give me the DDR controller register and guide line document . ?

2 ) How to do DDR stress test on IMX8qm Rev : B device. ?

[arunkvnss]

Dear NXP Expert,

I would like inform you some progress on the debugging.

As you said, I able to flash the latest NXP release, And found it is not able to read the UBOOT from SPL it comes with "mmc read error", We give 1.8V to the SD cards IO. So 3.3v is not supplied to the IO lines. I feel this might be the reason why it stuck at mmc read. Hence I need to configure the SPL for working at High speed. (In normal speed it expects 3.3V, and high speed 1.8 V is enough) . Is this achievable ? . Where i need to change in SPL source code ?

[arunkvnss]

Any input on this ?

[arunkvnss]

Hi NXP expert

Could you share the IMX8QM Rev B0 , 1.2 MHz, 800 MHz DCD Header file ?

[arunkvnss]

Any Input ?

[arunkvnss]

Dear NXP Expert,

I have gone through the sheet, Do you have any suggestions for my problem ?. My device is booting some times and will get stuck at some place (kernel). Most of the time, It Stuck at SPL where it copies U-boot to DDR. What could be the issue. ? Which parameter of DDR needs to be configured again. As far as i know all parameters are as per the JDEC standard.  How can i figure out this problem. ?

[igorpadykov]

suggest to rebuild all image from scratch, using latest RPA tool and last kernel

described in   https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applicat...

Best regards
igor

[igorpadykov]

Hi arunkvnss

such changes can be performed with  MX8QM_B0_LPDDR4_RPA_1.6GHz_v21.xlsx

tool found on below link. Also one can find there ddr tool and all documentation.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8-8X-Family-DDR-Tools-Release/ta-p/...

Best regards
igor

[arunkvnss]

Dear NXP Expert,

Let me attach my logs for your reference. As i told you before, I could able to boot up my one board successfully,The issue is happening only in the Another board, We use the same software, But it stucks after SPL. Please verify the logs given below.

SCFW logs...

parm=0 rtn=0
rtn=2
board_init(0)
board_init(1)
!!!!!!!!!!!!!!!!
board_config_sc
board_init(4)
board_init_ddr(0)
SCFW with Delay: 300 us
DDR frequency = 1596000000
board_system_config(0, 0)
!!!!board_early_cpu!!!!!!
board_init(5)
!!!!board_early_cpu!!!!!!
board_init(2)
@@@@@@@@@@@@@@@@@
pmic_init
ROM boot time = 211960 usec
SCFW boot time = 68976 usec
Banner = 14 usec
Init = 3443 usec
Config = 5947 usec
DDR = 6485 usec
SConfig = 2120 usec
Prep = 47785 usec
parm=1 rtn=0
rtn=26
parm=2 rtn=0
rtn=1 

Another console (For Uboot/kernel)

U-Boot SPL 2018.03-imx_v2018.03_4.14.98_2.0.0_ga+g87a19df (Sep 30 2020 - 15:40:42 +0000)
Normal Boot
Trying to boot from MMC2_2
Load image from MMC/SD 0x4d800
U

It stucks here, But in another board we were getting Uboot/Kernel and root login. What could be the issue ?