I.MX8MQ JTAG Load SPL and UBOOT

[elcfd]

Hi All,

I am trying to load uboot into RAM via JTAG. Following this idea:

My process is as follows

1) Load and run SPL file

2) Allow SPL to init DDR

3) Load and run uboot

So far I can load the SPL and see the beginning of SPL running (output over serial console) however the DDR initialisation never completes. Is there something I am missing? Maybe I need to load more DDR files before running SPL file?

Thanks

[elcfd]

Hi Igor,

Thanks for the reply. Yes it passes the tests as it is a dev board and not a custom board.

I have a working uboot and OS for this board that I can boot into - this was built using Yocto.

I took the built uboot SPL and tried to boot using this over JTAG and this is where I am having problems. The fact that boots when booting from the eMMC suggest to me that I have missed something when using the same binaries to boot over JTAG.

Do you know what I could be missing? I am trying to get a working method where I can boot over JTAG in preparation for a custom board which doesnt have a USB type C connection and therefore I cant program using mfgtools/uuu.

Regards,

Charlie

[igorpadykov]

Hi Charlie

one can pay attention to firmware binaries for MCU based DDR PHY,
which needs to load DDR firmware before DDR initialization described
in sect.4.3 Building u-boot image MSCALE_DDR_Tool_User_Guide.pdf
included in ddr test package.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...

Best regards
igor

[elcfd]

Hi Igor,

So I have had some success by loading the pladdr4_pmu_train*.bin binaries as the ddr tool does before running the stress tests.

I am using openocd to do the following:

load_image lpddr4_pmu_train_1d_imem.bin 0xADDRESS

load_image lpddr4_pmu_train_1d_dmem.bin 0xADDRESS

load_image lpddr4_pmu_train_2d_imem.bin 0xADDRESS

load_image lpddr4_pmu_train_2d_dmem.bin 0xADDRESS

I have calculated the correct addresses by reading through the code in drivers/ddr/imx/imx8m/helper.c

When I then load and run SPL the training completes successfully. However, during the very last phase of ddr_init there is a call to dram_config_save function which causes the processor to reset. I think it is trying to access memory at CONFIG_SAVED_DRAM_TIMING_BASE which hasnt been initialised properly. This is confusing to me since the training seems to run successfully.

Am I using the correct method to load the training binaries via openocd and why is the dram_config_save function causing the processor to reset?

Many Thanks,

Charlie

[igorpadykov]

Hi Charlie

for debugging with jtag one can look at

https://community.nxp.com/t5/i-MX-Processors/How-to-JTAG-debug-iMX8mq/m-p/837227

Unfortunately ddr training procedure is not simple or straightforward and there is currently no

documentation how to do it via jtag. In particular processor DDR PHY contains it's own

MCU to which a firmware and set of input parameters needs to be loaded in order to get it running.

Best regards
igor

[igorpadykov]

Hi elcfd

had board passed ddr test:

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...

necessary uboot changes are described in Chapter 4 How to bring up a new MX8MSCALE board

MSCALE_DDR_Tool_User_Guide.pdf  included in ddr test package.

Best regards
igor