Hi,
I have a project where I need to stream a video on a 8 bit parallel BT.656or 8 to 16bit width parallel bus with explicit sync signal.
I am looking at the section 13.2 of the "i.MX 8M Nano Applications Processor Reference Manual" and need to know if its possible and what are the limitation.
Option 1:
BT.656 possible on a 8bit width bus but at what frequency.
Option 2: "most interesting"
using LCDIF in VSYNC Mode
How width can the data bus be? only 8 or up to 16?
the max frequency is set by DISPLAY CLOCK (pix_clk) = DISPLAY_PIXEL_CLK_ROOT = maximal frequency is 250Mhz
what are to GPIO use to output those signal.
Please correct me if I'm wrong or missing something.
Thanks :smileyhappy:
Hello frederic,
Sorry for our delay reply! Below is feedback from i.MX Expert:
----------------
The data path is LCDIF DPI --> MIPI DSI CORE --> mipi phy --> MIPI panel. There is no parallel interface to lcd panel.
Max of LCD_DOTCLOCK is 250M.
It is DOTCLK mode lcdif supports for MIPI-DPI interface.
8bit is supported.
-------------------
Hope above information is helpful to you!
B.R,
Weidong