I.MX6 PCIe power-on initialization sequence

[jiandong1]

Hi，NXP:

We have measured the PCIe power-on initialization sequence of EVK（FW version：LF_v5.15.32-2.0.0_images_IMX6QPDLSOLOX），PCIE_RESET active before PCIE_CLK about 1ms，details as attachment；

According to the PCIe design specification，when PCIE_CLK is stable，PCIE_RESET just active ，now PCIE_RESET active before PCIE_CLK，so I want you to clarify the issue，thanks for your reply~

[jiandong1]

Done，Thanks~

[jiandong1]

Done，Thanks ~

[Zhiming_Liu]

Hi @jiandong1 

This is Synopsys DesignWare PCI IP requirements.

Best Regards

Zhiming

[jiandong1]

Thank you~

By the way，could you support some related files for study？

[Zhiming_Liu]

The IP SPEC can't share.

[jiandong1]

ok，thanks~