How to verify modified ddr clock frequency value is set?

[gbiradar]

Hi Guys,

                 i'm using memtool to read 0x020c4018 register. in uboot source code i have changed macro from 396MHz to 333MHz now i got some value how do i verify it is 333MHz?

regards,

Ganesh

[timbraun]

One very simple scope-less option I recently used is to time iterations of the u-boot mtest command. Test a few GB of ram and time the laps. In my case,

mtest 0x10000000 0x8e000000 0xaa5555aa 100

Each iteration took about 10 sec with a 1066 MHz DDR clock, and I verified a slower clock setting with a longer iteration time.

[MOW]

Hi Ganesh

If you have an oscilloscope with a sufficiently high bandwidth and you're using some eval-board have a look at the schematics: e.g. the Sabre-AI, -SDB, and -SDP boards all have shunt-resistors on the DRAM-SDCLK signals, which you can use to measure the clock directly going to the RAMs instead of having to configure the CLKO1,2 signals.

The CLKO-approach does have the benefit, though, that you can use a cheaper oscilloscope, as well, because you can output a scaled-down version (up to "div by 8") of the clock.

Regards,

Marc

[igorpadykov]

Hi Ganesh

one can output it on clko1,2 signal using CCM_CCOSR register (select

mmdc_ch0_clk_root) and measure with oscilloscope.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[gbiradar]

Hi igorpadykov​

          their lies the problem i have oscilloscope which support upto 300MHz only. if you know any other way please tell.

other wise can you give me register value for 333MHz, 400MHz.

NOTE: i have lpddr2 register aid -> if i change frequency to 333MHz 0x020c4018 register is not changing.

[MOW]

Hi Ganesh

In the CCM_CCOSR register you can also configure integer dividers from 1 up to 8 for the output clock signal, so you can use slower oscilloscopes to measure the DDR clock, as well.

Regards,

Marc