How to use the DDR tool for i.MX8M with DDR3L

[george]

Dear OliverChen‌,

We use i.MX8M and DDR3L for our product.

The DDR3L(MT41K512M8DA-107 IT:P) is 8-bit width. That is, in order to take 32-bit width, we using 4 x DDR3L.

    - https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf

We performed the calibration using DDR tool and Aid Script which you posted.

   - i.MX8MSCALE DDR Tool Release 

   - Aid Script which we edited is attached below.

However, it Fail in DDRPHY training.

PMU: Error: Dbyte 0 nibble 0 rxClkDly passing region is too small (width = 0)

PMU: ***** Assertion Error - terminating *****

What does this mean?

Please tell me how to avoid this.

Best Regards,

George

[oliver_chen]

Hi george‌,

From the output message, the read DQ deskew training result in lower bits(3:0) of data byte[7:0] don't have enough margin, and training is failed.

PMU is referred to DDRPHY MCU.

dbyte0 is data[7:0]

nibbble0 is data[3:0]

B.R

Oliver

[george]

Dear OliverChen‌,

Does the read DQ deskew training which you say mean the Data Eye Training?

Best Regards,

George

[oliver_chen]

Yes

B.R

Oliver

[george]

Dear OliverChen‌,

It seems that Aid-Script has an issue.

The cell shown by the following picture should be updated according to the value in Register Configuraton Sheet.

We are setting 0x1 as the cell, and the calibration has been completed correctly.

Best Regards,

George

[oliver_chen · Accepted solution]

Hi George,

How many chip select do you have? If there are two chip selects in your board and you configure csPresent to 1, it means you only calibrate the CS0 and the DDR rank0 is OK, but the DDR rank1 (CS1) has some problems. If there are only one chip select in your board, yes, you must configure csPresent to 1.

B.R

Oliver

[george]

Dear Oliver,

Yes, Our board uses one chip select.

And, I saw the substitution formula of the cell modified in the new version.

Thanks,

George