How to use LPUART2 polling example on CM33?

[wendy-liu]

Dear all,

      I want to use lpuart polling example on SDK, the demo_example is LPUART1, but I want to use LPUART2.

     Then I add pin_mux and set the clock, then debug console print as below:

ASSERT ERROR " (reg & PCC_CLKCFG_PR_MASK) != 0UL ": file "/home/wendy/workspace/imx8ulp-m33/devices/MIMX8UD7/drivers/fsl_clock.c" Line "300" function name "CLOCK_SetIpSrc"

    This is my add:

void BOARD_InitHardware(void)

{

    +CLOCK_SetIpSrc(kCLOCK_Lpuart2, kCLOCK_Pcc2BusIpSrcFusionDspBus);

 }

void BOARD_InitPins(void) {                                /*!< Function assigned for the core: Cortex-M33[cm33] */

    IOMUXC_SetPinMux(IOMUXC_PTA10_LPUART1_TX, 0U);

    IOMUXC_SetPinConfig(IOMUXC_PTA10_LPUART1_TX,

                        IOMUXC_PCR_PE_MASK |

                        IOMUXC_PCR_PS_MASK);

    IOMUXC_SetPinMux(IOMUXC_PTA11_LPUART1_RX, 0U);

    IOMUXC_SetPinConfig(IOMUXC_PTA11_LPUART1_RX,

                        IOMUXC_PCR_PE_MASK |

                        IOMUXC_PCR_PS_MASK);

    +IOMUXC_SetPinMux(IOMUXC_PTB2_LPUART2_TX , 0U);

    +IOMUXC_SetPinConfig(IOMUXC_PTB2_LPUART2_TX ,

    +                    IOMUXC_PCR_PE_MASK |

    +                    IOMUXC_PCR_PS_MASK);

    +IOMUXC_SetPinMux(IOMUXC_PTB3_LPUART2_RX, 0U);

    +IOMUXC_SetPinConfig(IOMUXC_PTB3_LPUART2_RX,

    +                    IOMUXC_PCR_PE_MASK |

    +                    IOMUXC_PCR_PS_MASK);

}

Looking forward to your reply!

Thanks!

[wendy-liu]

I add clock in ATF: plat/imx/imx8ulp/imx8ulp_bl31_setup.c:

mmio_write_32(0x28102000+ 0x2c, 0x80000000);

But it doesn't work

[danielchen]

Hi @wendy-liu :

LPUART2 is in DPS domain,  is designed for DSP core, not for CM33.  CM33 can not control it.

please check the reference manual.

Regards

Daniel

[danielchen]

LPUART0 and LPUART1 are in CM33 real time domain.

[wendy-liu]

I know, but how to enable LPUART2 on DSP domain?

[danielchen]

Hi @wendy-liu :

The error message is from function CLOCK_SetIpSrc, can you debug and check the value of reg?

Regards

Daniel

[wendy-liu]

The reg of PCC_LPUART2 is always 0.  

[danielchen]

Please try below lines.

    const cgc_rtd_sys_clk_config_t g_sysClkConfigFroSource = {

    .divCore = 0, /* Core clock divider. */

    .divBus  = 1, /* Bus clock divider. */

    .divSlow = 3, /* Slow clock divider. */

    .src     = kCGC_RtdSysClkSrcFro, /* System clock source. */

    .locked  = 0, /* Register not locked. */

};

    CLOCK_SetFusionSysClkConfig(&g_sysClkConfigFroSource);

     BOARD_InitPins();

     BOARD_BootClockRUN();

     BOARD_InitDebugConsole();

     Fusion_Init();

     BOARD_SetTrdcGlobalConfig();

    rate = CLOCK_GetFreq(kCLOCK_FusionDspBusClk);

    PRINTF("The rate is 0x%x. \r\n", rate);

      CLOCK_SetIpSrc(kCLOCK_Lpuart2, kCLOCK_Pcc2BusIpSrcFusionDspBus);

Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design.  Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

[wendy-liu]

I have tried it.

The rate is 0x5b8d800. My M core and A core don't start normally...

There is my patch.

[danielchen]

Hi @wendy-liu :

Did you solve this issue now?

[wendy-liu]

I have already enabled LPUART2, but I'm having some issues with API “LPUART_WriteBlocking” I'm currently using.

[danielchen · Accepted solution]

Thanks for your update.  please follow below thread for this question.  Re: imx8ulp m33 core gpio - NXP Community

[wendy-liu]

yes, I read reg of LPUART1  and LPUART2 CLOCK, result is 0xd2000000 and 0.

Now, I 'm working with TRDC for eDMA access.

I add some configutation in 

voidBOARD_SetTrdcGlobalConfig(void) as below:

        /* non secure state can access lpuart2(PBridge2 slot 11, T-MBC3) for eDMA0 */

        mbcBlockConfig.memoryAccessControlSelect = TRDC_MBC_ACCESS_CONTROL_POLICY_ALL_INDEX;

        mbcBlockConfig.nseEnable                 = true; /* non secure state can access the block for eDMA0 */

        mbcBlockConfig.mbcIdx                    = 3U;   /* MBC3 */

        mbcBlockConfig.domainIdx                 = TRDC_DMA0_DOMAIN_ID; /* MBC3_DOM0 */

        mbcBlockConfig.slaveMemoryIdx            = 0U;                  /* MBC3_DOM0_MEM0 */

        mbcBlockConfig.memoryBlockIdx            = 11U;                 /* MBC3_DOM0_MEM0_BLK_CFG_W11 */

        TRDC_MbcSetMemoryBlockConfig(TRDC, &mbcBlockConfig);

But the result is that I don't read reg of LPUART2[PCC_REG(kCLOCK_Lpuart2)]. It means the Peripheral is not present...

Is there any new information on this?

[danielchen]

did you initialize the DSP core (Fusion_Init) before you call CLOCK_SetIpSrc?