How to setup devicetree for iMX6QP to get lvds-display work?

[elmaralbert]

I have a custom board, which is running well with an iMX6DL, including lvds-display. Since about two or three weeks I try to setup the same custom board with an iMX6QP mounted. With some adaptations, linux is booting (yocto morty), but no lvds-clock and so nothing on the display.

How to setup the lvds-interface on the iMX6QP (lvds channel 1)? Where are the big differences between iMX6DL and iMX6QP setup?

[igorpadykov]

Hi Elmar

i.MX6QP significantly differs from i.MX6DL, one can look at

EB810 i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus Applications Processor Comparison 

http://cache.nxp.com/docs/en/engineering-bulletin/EB810.pdf 

For i.MX6QP lvds one can check imx6qp.dtsi

linux-imx.git - i.MX Linux Kernel 

Demo Images

http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0_MX6QDLSOLO&appType=license&location=null&Pa... 

Best regards
igor
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[elmaralbert]

Hi Igor,

thank you very much for your answers to my questions and excuse me for my late response.
I tried to bring my devicetree into linux-imx using the branch boundary-imx_4.1.15_2.0.0_ga
(previously took over the software from an earlier colleague: kernel V4.9.0).

After solving all the build and runtime issues, linux V4.1.15 is now booting using the mxc-ipu driver,
but with no success regarding the lvds-interface.
The problem seems to be that I get no handle from the function mxc_dispdrv_gethandle.
I wonder how this function works at all as it never enters the loop

            list_for_each_entry(entry, &dispdrv_list, list) {...

I guess there is something additionally missing in my device tree. I compared it with e.g. the
imx6qp-sabresd.dts and took over some entrys (mxcfbxx).

I see that mxcfb_probe and thereafter mxcfb_dispdrv_init is called, but as mentioned, no handle and so
mxcfb_dispdrv_init returned with -19 (-ENODEV).

Would it be possible to send my devicetree-files to you and you may have a short view on it and and you give me a hint?
And if so, how can I send it to you, as I didn't find a way to attach a file here.

Thank you in advance and best regards
Elmar

[igorpadykov]

Hi Elmar

boundary-imx branch and kernel V4.9.0 is not supported by nxp,

it is supported by boundary devices (boundarydevices.com),

below description of official nxp bsps

http://www.nxp.com/products/software-and-tools/software-development-tools/i.mx-software-and-tools/i....

Best regards
igor

[elmaralbert]

Hi Igor,

thank you very much.

Now I’m using the branch imx_4.1.15_2.0.0_ga and after some adaptations in the devicetree I have my display running.

But I still have a problem regarding the lvds clock, which is to high; I don’t see my expected frequency and cannot adjust it, also it seems it will be correctly fetched from the devicetree as I can see in of_get_display_timings.

I found a post in the community, which describes a very similar problem here:

https://community.nxp.com/thread/444292

It was also answered by you. I applied the patch you attached there, but with no success. Unfortunately in the mentioned post, there is no further response from Charles, whether the attached patch is working on his side or not.

With the patch applied I see 001 (derive clock from PLL2 PFD0) for ldb_di0_clk_sel and ldb_di1_clk_sel in register CCM_CS2CDR. On my working board with an iMX6S mounted these values are 000 (pll5 clock).

When I revert the patch and make the changes Charles mentioned in his post (in arch/arm/mach-imx/clk-imx6q.c), then it also works fine for me; i.e. I see my expected lvds-clock frequency. The values for for ldb_di0_clk_sel and ldb_di1_clk_sel in register CCM_CS2CDR are 000.

As I’m new on iMX6 and especially on iMX6QP I’m not really familiar with the clock-adjustment and it confuses me a bit. When deriving ldb_di clock different from pll5, then the clock frequency will not be adjusted as expected. Maybe you can give me a further hint.

Thank you in advance and best regards

Elmar

[igorpadykov]

Hi Elmar

may be useful to check EB821 LDB Clock Switch Procedure & i.MX6 Asynchronous

Clock Switching Guidelines

http://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf 

Best regards
igor

[elmaralbert]

Hi Igor,

I checked the the file http://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf 

It seems to me, that the described procedure to adjust the LDB clock is implemented within the functions “disable_anatop_clocks();” and “init_ldb_clks(np);” in file arch/arm/mach-imx/cpuidle-imx6q.c.

But I wonder why these are no used for the QuadPlus!

if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {

     clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);

     clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);

} else {

    /*

     * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware

     * bug. Set the muxes to the requested values before registering the

     * ldb_di_sel clocks.

     */

     disable_anatop_clocks();

     init_ldb_clks(np);

     clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));

     clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));

}

Further down the file, the parent clock for IMX6QDL_CLK_LDB_DI0_SEL and IMX6QDL_CLK_LDB_DI1_SEL is set fix to IMX6QDL_CLK_PLL2_PFD0_352M.

if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {

    imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);

    imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);

}

What is the reason for this implementation for the iMX6QP?

In our application we use PLL5 for IMX6QDL_CLK_LDB_DI0_SEL and IMX6QDL_CLK_LDB_DI1_SEL.

Now I understand why it was not working with the original version of cpuidle-imx6q.c as PLL5 never was selected.

There are two ways the achieve this. Either setting the clock fix to PLL5 using IMX6QDL_CLK_PLL5_VIDEO_DIV or, what I prefer, using “disable_anatop_clocks();” and “init_ldb_clks(np);” and remove (set to comment) the fix adjustment. With this there is a dynamic way to set IMX6QDL_CLK_LDB_DI0_SEL and IMX6QDL_CLK_LDB_DI1_SEL by adding

&clks {

    fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;

    fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;

};

to the device tree, which I found in e.g. imx6qdl-sabresd.dtsi.

This is working fine for me, but the remaining question to me is, what is the NXP recommended way the adjust the MUX for the iMX6QP. Is it that described in http://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf ?

I guess – yes, as I think this document is valid for all iMX6 derivates, isn’t it?

Further I did not find differences between the QP and SOLO reference manuals in the CCM chapter regarding the MUX adjustment. Maybe I have overseen something important?

It would be of great help to me, if you could give me a comment about that.

Now I will go on the displaying images and playing videos and will come back to you if there are additional issues:-)

Thank you in advance and best regards

Elmar

[igorpadykov]

Hi Elmar

you are right, EB821 is applicable to all i.MX6 derivatives.

For differencies i.MX6QP and i.MX6Q one can look at EB810

http://cache.nxp.com/docs/en/engineering-bulletin/EB810.pdf 

Unfortunately there is no special document with differences between the QP and SOLO.

Best regards
igor

[veeraiyanchidam]

Hi @igorpadykov ,

We are facing is an issue with respect to LVDS clock in iMX6QP. 

In Quardplus if ldb driver tries to set frequency 33.3 MHz it gets wrong frequency or it stays back with previous frequency. In iMX6QP LDB Clock sourced from PLL2_PFD0_352M but for other boards LDB Clock sourced from PLL5_VIDEO , this Clock sources differences is not  explanation any where in the FSL document. To fix this Quardplus LDB Clock sourced from PLL5_VIDEO.

Could you please tell us why iMX6Qp LDB Clock sourced from PLL2_PFD0_352M and why setting of  frequency is failing ?.