AnsweredAssumed Answered

Can't change LVDS clock source on imx6qp

Question asked by charles huang on Feb 8, 2017
Latest reply on Feb 10, 2017 by igorpadykov

Hi

On Yocto 2.1

I want to porting a LVDS panel , but clock frequency is too high , so I must modify as below:

 

&clks {
   fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
   fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};

 

it works well on imx6q, but I found that can't work on imx6qp

 

So I trace code ,and find code as below in arch/arm/mach-imx/clk-imx6q.c

if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
    clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels,    ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
    clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,    ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
} else {
/*
* The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
* bug. Set the muxes to the requested values before registering the
* ldb_di_sel clocks.
*/
   disable_anatop_clocks();
   init_ldb_clks(np);
   clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels,    ARRAY_SIZE(ldb_di_sels));
   clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,    ARRAY_SIZE(ldb_di_sels));
}

 

If I remove above code with delete line, it works well 

Why don't need to init ldb clk on imx6qp? What's difference ?

Please help us,thanks

Outcomes