How to set CPU frequency on u-boot?

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How to set CPU frequency on u-boot?

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LiLinfei
Contributor I

Hi,

How to set CPU frequency on u-boot?

Our machine must keep working at 800Mhz.But I see the frequency under U-boot is 396Mhz.

U-boot version : 2016.03

SOC:IMX6ULL 

Thanks!

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tomas-paukrt
Contributor I

I dealt with the same issue on U-Boot 2025.10 and ended up with this solution:

#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>

int board_early_init_f(void)
{
  struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

  /* exit if the CPU does not support 792 MHz */
  if (get_cpu_speed_grade_hz() < 792000000)
    return 0;

  /* increase VDD_SOC from 1.150 V to 1.175 V */
  set_ldo_voltage(LDO_SOC, 1175);

  /* increase VDD_ARM from 1.150 V to 1.225 V */
  set_ldo_voltage(LDO_ARM, 1225);

  /* increase ARM clock from 396 MHz to 792 MHz */
  writel(0, &imx_ccm->cacrr);

  return 0;
}

 

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joanxie
NXP TechSupport
NXP TechSupport

you can find the cpu frequency settings in the dtsi file as below:

"https://source.codeaurora.org/external/imx/uboot-imx/tree/arch/arm/dts/imx6ull.dtsi?h=imx_v2019.04_4..."

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avijitnsec
Contributor III

How to change the default frequency in the dts file? If I set it in the uboot, does it persist when kernel boots up? Or kernel overwrite the value? 

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AlfTeleco
Contributor III

On the U-boot version U-Boot 2021.04-lf_v2021.04 write the CCM Arm Clock Root Register (CCM_CACRR) at the function get_mcu_main_clk() on the file /arch/arm/mach-imx/mx6/clock.c. The content of the function must be like this:

=====================================================================

u32 reg, freq;

reg = __raw_readl(&imx_ccm->cacrr);
reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
__raw_writel(reg, &imx_ccm->cacrr);

reg = __raw_readl(&imx_ccm->cacrr);
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
freq = decode_pll(PLL_SYS, MXC_HCLK);

return freq / (reg + 1);

=====================================================================

We are setting the register CCM_CACRR to have NO divider, like it is said in the datasheet:

AlfTeleco_0-1707405319109.png

Also boost the LDO_SOC voltage from 1.175 to 1.225 at the function /arch/arm/mach-imx/mx6/soc.c: board_postclk_init()

set_ldo_voltage(LDO_SOC, 1225); /* Set VDDSOC to 1.225V */

 

BR

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