How to reset core0 with new program on imx6 SoloX

[hansriekehof-bo]

Hi there,

this might sound a little weird but i want to reboot just the A9-Core on an imx6-SoloX from a running M4-program. The M4-Core should not be reset and kept running after this. So basically i want to reload a different program image from the m4 core to the a9 core.

I found in the SRC_SCR register, that there is a core0_rst bit. But its not clear to me what exactly happens when i assert this bit. What i know so far is, that my program running on the m4 core crashes immediately so there must be happening something which i do not expect or understand.

I thought the core0 jumps to the boot code (Address 0x0) and if i enabled warm_reset in the SRC the core0 should than jump to the address in SRC_GPR0 (PERSISTENT_ENTRY0) to execute code. But this doesn't happen as it seems and i don't know why exactly.

Does anyone have some hints on this matter on how i could do this ?

What does the core0_rst bit in the SRC really do when asserted ?

Best,

Hans 

[Carlos_Musich]

Hi Hans,

Unfortunately it is not possible to reset only A9 and keep working with M4. As you can see in Reference Manual, A9 is in charge to configure and start M4. So if A9 is reset the M4 will be also reset and reconfigured.

13.5 Cortex-M4 Boot Requirements
• Cortex-A9 always boots as the primary core.
• Cortex-M4 does not have a boot ROM and at POR is not provided a clock
• Cortex-A9 user code is responsible for the following:
• Loading and authenticating Cortex-M4 firmware by HAB API or with Cortex-
A9 firmware together as a unified image by boot ROM.
• Launching the Cortex-M4 by enabling its clock and clearing its reset bit in SRC
(See System Reset Controller Chapter for more details).

Best regards,
Carlos

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[hansriekehof-bo]

Hi Carlos,

i think this is true for POR or a cold reset as it is called in the manual. In this case the A9 always boots first und you have to setup the m4 from the A9.

But in the chip there is a possibility in for a warm_reset. See chapter 61.6.1.2.5.

There is also a possibility for the A9 to continue at a specific address after waking from a low power mode. See 61.7.7 

Also the diagram of the high level boot sequence (8.2.2) shows, that there is a possibility in the boot code to avoid all the image checking and chossing the boot device etc. and directly jump to an specific address. 

So i think there seems to be a way to reboot the A9 core without resetting the whole chip.

Do you have some more explanations for me what the core0_rst bit does in the SRC ?

Best,

Hans 

[Carlos_Musich]

Hi Hans,

it is true that for the A9 to continue at a specific address after waking from a low power mode but not after reset, even warm reset.

As you can see in chapter 8.2.2 High-level boot sequence it refers to check the CPUID from 0 to 3. This is a general case for i.MX6 processors which can have up to 4 A9 cores and core0_rst refers to this boot sequence but it is not the case with A9 and M4.

Best regards,
Carlos

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