How to prevent 125 MHz Clock Reference causing conflict on 50 MHz Clock input for RMII

[dougbailey]

I have a board that I am developing that is based on the SabreSD card using an iMX6DL CPU. It is running a Linux kernel based on the NXP fsl-yocto-L4.1.15_2.0.0-ga BSP. I have taken the SabreSD device trees and modified them for use with my board.

One difference on my board is that the Network Interface is using an RMII interface in which the 50 MHz reference that is being driven by the PHY and is incoming on GPIO_16.

I was having an issue where the CPU was not inputting the 50 MHz reference clock but was instead outputting a 125 MHz (resulting in contention on the clock line.) I diagnosed the problem to the setting of the ENET_CLK_SEL (bit 21) of the IOMuxc GPR1 register being set by the kernel.

The pin is set by a call made in the imx6q_1588_init function of arch/arm/mach-imx/mach-imx6q.c. I don't see any easy way that prevents this function from setting this bit.

Does anyone have an idea as to how to prevent this pin from being set via the device tree?

Is there any way of preventing this from happening other than patching the source code?

Patch to clear ENET_CLK_SEL bit in IOMuxc GPR1
========================================
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index ae5c3cd..d878c323 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -220,7 +220,7 @@ static void __init imx6q_1588_init(void)
    if (!IS_ERR(gpr))
        regmap_update_bits(gpr, IOMUXC_GPR1,
                IMX6Q_GPR1_ENET_CLK_SEL_MASK,
-               IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+              IMX6Q_GPR1_ENET_CLK_SEL_PAD);
    else
        pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

[art · Accepted solution]

This function seems not to be reflected in the device tree configuration, so, there seems to be no way of configuring the GPIO_16 pin as the RMII ENET_REF_CLK signal other than patching the source code.

Have a great day,
Artur

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