We use the iMX7D with Linux in a design where we need to separate SAI ports as I2S interfaces.
One is used as input (SAI1) from ADCs with a master clock of 16.777216MHz and the other (SAI3) is used as output to a DAC with a master clock of 8.388608MHz (16.777216MHz/2). Both ports running simultaneously.
The base clock for the MCLKs is an 16.777216MHz precision oscillator connected to CCM_CLK2 input.
How do I setup these 2 different MCLKs?
Any further documentation on this subject would be appreciated.
已解决! 转到解答。
Hi Thomas
sorry for delay, issue was investigated internally, below summary:
"So in conclusion audio_mclk_root_clk clock is taken all the time by SAI1 module even
if is configured to work through IMX7D_SAI1_ROOT_CLK and for this reason it was not
possible generate 2 different clock sources in SAI modules.
This behavior is the same your costumer is facing."
Best regards
igor
Hi Thomas
sorry for delay, issue was investigated internally, below summary:
"So in conclusion audio_mclk_root_clk clock is taken all the time by SAI1 module even
if is configured to work through IMX7D_SAI1_ROOT_CLK and for this reason it was not
possible generate 2 different clock sources in SAI modules.
This behavior is the same your costumer is facing."
Best regards
igor
Hi Igor,
thank you for you help. It was not the answer we hoped for or originally expected and we have to make hardware changes to work around this undocumented limitation.
I hope there will soon be an update to the datasheet and reference manual.
I beleive the iMX7 documentation needs a thorough update. I have read to many references to the iMX6 documentation for questions regarding iMX7.
Thomas
Hi Thomas
SAI (MSEL) MCLK clock select must be either 0 or 1, these inputs are tied together.
The SAI MCLK always comes from the SAIx_CLK_ROOT, so seems there is no much
flexibility for generating 2 different MCLKs.
Best regards
igor
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Hi Igor,
thank you for your quick answer. I'm just not sure I understand it correctly.
Below you can see some of our clock tree made with a clk_summary tool.
In your answer you say that SAI MCLK always comes from SAIx_CLK_ROOT and as you can see we have 2 of these.
SAI1_CLK_ROOT 16.777216MHz
SAI3_CLK_ROOT 8.388608MHz
We have had no luck gating these clocks out on the MCLK pins. But we also have an AUDIO_MCLK_ROOT_CLK, and it is this clock that we see on both MCLK outputs. We have tried changing the AUDIO_MCLK_ROOT_CLK frequency and can see the changes on both MCLK outputs.
If what you say about "SAI MCLK always comes from the SAIx_CLK_ROOT" is true, then it seems we can generate 2 different clocks but how do we route these to the pins?
And why do we see the AUDIO_MCLK_ROOT_CLK on the pins?
Hi Thomas
please check Table 5-11. Clock Root Table i.MX7D Reference Manual
http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf
there are SAI1_CLK_ROOT, SAI2_CLK_ROOT.
There is no "AUDIO_MCLK_ROOT_CLK".
Best regards
igor
Hi Thomas
Best regards
igor
Hi Igor,
you write that -
"AUDIO_MCLK_CLK can be used for generation SAI MCLK using appropriate MSEL settings, like in Vybrid processors, but not in i.MX7D"
and in your first answer you write that -
"SAI MCLK always comes from the SAIx_CLK_ROOT"
but we ONLY see the AUDIO_MCLK_CLK on the MCLK pins of both SAI1 and SAI3 and not the SAIx_CLK_ROOT clocks, contrary to both your statements.
No matter what we try we can't get the SAIx_CLK_ROOT out to the pins.
We have tried with all 4 possible MSEL setting but this only changes things for the bit clock. MCLK is still AUDIO_MCLK_CLK, but for MSEL settings 0x10 and 0x11 the bit clock disappears.
Best regards
Thomas
Hi Thomas
how did you determine that "we ONLY see the AUDIO_MCLK_CLK on the MCLK
pins of both SAI1 and SAI3 " , how had you verified this ? Had you checked signals
with oscilloscope. Could you try to set up clocks without linix in baremetal setup.
One can try for example gate sai1 clock (CCM_CCGR140, use Table 5-19. CCGR Mapping Table
i.MX7D RM) and check if MCLK of SAI1 will stop.
MSEL selection must be either 0 or 1, these inputs are tied together. The SAI MCLK always comes from the SAIx_CLK_ROOT.
This is answered by design team.
Best regards
igor
We determined that it was AUDIO_MCLK_CLK by having setup the different clock as shown below
AUDIO_MCLK_CLK - 4MHz
SAI1_CLK_ROOT - 16MHz
SAI3_CLK_ROOT - 8MHz
and then measure the frequency on both MCLK pins (SAI1 and SAI3). We measured 4MHz on both, with all tested settings.
We have now tried setting CCM_CCGR140 to 0x0 10ms after previous settings where enabled, and this stopped the bit clock but did not change the MCLK frequency which is still equal to AUDIO_MCLK_CLK.
Best regards
Thomas
could you try to set AUDIO_MCLK_CLK to 24MHz -
AUDIO_MCLK_CLK_ROOT = 000 - OSC_24M using Table 5-11. Clock Root
Table i.MX7D RM and check if this change MCLK SAI to this frequency.
Best regards
igor
Hi Thomas
there are no sai_mclk, there are only csi_mclk - it is different signal.
There are only sai1_root_clk=16MHz, sai3_root_clk=8MHz as expected.
Can you confirm that SAIn_MCLK signals were verified with oscilloscope and
it changed to 24MHz.
Best regards
igor
Hi Igor,
I can confirm that the clocks on the SAI MCLK pins was 24MHz after setting the AUDIO_MCLK_ROOT_CLK to OSC clk 24MHz.
Does your sentence "there are no sai_mclk, " mean that there are no such clocks in the chip or do you refer to our clock tree?
I only send you part of the clock tree to show the clocks in question, but I can send you the full clock tree for reference if you like.
Thomas
Hi Igor,
the board is our own custom board and the BSP used is from the iMX7D Sabre EVM board offcouse with our own modifications to fit our board. The SAI driver we use is also based on the Sabre board BSP but with many modifications.
The processor marking reads -
MCIMX7D5EVM10SC
2N09P
NB3YGMB U1642
Korea
Thomas
Hi Thomas
I am going to elevate it, for that it is necessary to