Hi ,
refer to the page 2216 of IMX 28 RM
The reason for the transfer completion (clearing the Active bit) determines the next state.
• CErr field decrements to zero. When this occurs the Halted bit is set to one and
Active is set to zero. This results in the hardware not advancing the queue and the
pipe halts. Software must intercede to recover.
• The device responds to the transaction with a STALL PID. When this occurs, the
Halted bit is set to one and the Active bit is set to zero. This results in the hardware
not advancing the queue and the pipe halts. Software must intercede to recover.
• The Total Bytes to Transfer field is zero after the transaction completes.
• For a zero length transaction, it was zero before the transaction was started.
When this condition occurs, the Active bit is set to zero.
• The PID code is an IN, and the number of bytes moved during the transaction is less
than the Maximum Packet Length. When this occurs, the Active bit is set to zero and
a short packet condition exists. The short-packet condition is detected during the
Advance Queue state. Refer to Split Transactions for additional rules for managing
low- and full-speed transactions.
I want to know how to make the usb driver complete the usb bulk transfer without the above condition and make the host controller to update transfer result.
Hi liu
seems it is necessary to implement driver so number of bytes
moved during the transaction = Maximum Packet Length.
Since described behaviour occurs at errors during the transaction,
more useful approach would be to implement usb physical interface
in such way so less errors occur, please check layout rules in
i.MX6 System Development User’s Guide sect.3.11 USB recommendations
http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf
Best regards
igor
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Hi,
thanks very much!
It seems that the section 3.11 descript the hardware layout rules of USB.I think my issue is unrelated of hardware.It looks more like IC or driver issue.