How to know which pin triggered the interrupt with i.MX6?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

How to know which pin triggered the interrupt with i.MX6?

Jump to solution
731 Views
martindenion
Contributor II

I'm working on interrupts with i.MX6 processor.

As @RodBorras said in this thread:

"This is my understanding of how the MX6Q GPIO interrupts work:

a) GPIO1 (32 pins) through GPIO7 (32 pins) can be configured to generate interrupts when the pins are set to inputs

b) GPIO2 through GPIO7 do not have an "ARM interrupt" for each pin, but rather for the OR'ed results of 16 pins

    ==> e.g. GPIO2 will cause an "ARM IRQ 100" if there is a valid interrupt on any pin within 0-15

    ==> e.g. GPIO2 will cause an "ARM IRQ 101" if there is a valid interrupt on any pin within 16-31

    ==> So even though GPIO2 can monitor 32 pins for activity, the ARM Core will only see 1 of 2 IRQs happen (#100 or #101)

c) GPIO1 has the same functionality as described in b), but also some further granularity: its bottom 8 pins (0-7) will cause 8 specific "ARM interrupts"

    ==> GPIO1_0 will cause an "ARM IRQ 97", and so on for pins 1,2,3,4,5,6; GPIO1_7 will cause an "ARM IRQ 90"

    ==> for GPIO1_8 through GPIO1_31, these can only be seen through "ARM IRQ98" for pins 0-15, or "ARM IRQ99" for pins 16-31"


So if we take the example of two interrupts of the same group (for example, two pins between 0 and 15 of GPIO2), how can we know which pin triggered the interrupt?

Thanks for your help!

Labels (1)
0 Kudos
Reply
1 Solution
719 Views
igorpadykov
NXP Employee
NXP Employee

Hi Martin

 

interrupt source can be obtained reading GPIOx_ISR register

described in sect.28.5.7 GPIO interrupt status register (GPIOx_ISR)

i.MX 6Dual/6Quad Applications Processor Reference Manual

 

Best regards
igor

View solution in original post

0 Kudos
Reply
1 Reply
720 Views
igorpadykov
NXP Employee
NXP Employee

Hi Martin

 

interrupt source can be obtained reading GPIOx_ISR register

described in sect.28.5.7 GPIO interrupt status register (GPIOx_ISR)

i.MX 6Dual/6Quad Applications Processor Reference Manual

 

Best regards
igor

0 Kudos
Reply