How to fix DDR bus width with i.MX6DL-Sabre board

[torus1000]

Hi,
Now I try to check i.MX6S performance with i.MX6DL-Sabre board.
I think big difference between i.MX6S and i.MX6DL are core number and DDR bus width.
I only know how to disables one of dual core.

Does anyone know how to fix DDR bus width to x32?

Is it available to set 01 to MDCTL[DSIZ] after kernel bootup?
(Running change is OK for it?)

Thanks

[igorpadykov · Accepted solution]

Hi torus1000

DDR bus width can be set when DDR is initialized in Uboot

flash_header.S. It can not be changed after kernel bootup.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------