Hi,
I found the below information in the RM.
This PLL synthesizes a low jitter clock from the 24 MHz reference clock. The PLL has
one output clock, plus 3 PFD outputs. The System PLL supports spread spectrum
modulation for use in applications to minimize radiated emissions. The spread spectrum
PLL output clock is frequency modulated so that the energy is spread over a wider
bandwidth, thereby reducing peak radiated emissions. Due to this feature support, the
associated lock time of this PLL is longer than other PLLs in the SoC that do not support
spread spectrum modulation.
Spread spectrum operation is controlled by configuring the
CCM_ANALOG_PLL_SYS_SS register. When enabled, the PLL output frequency will
decrease by the amount defined in the STEP field, until it reaches the limiting frequency
in the STOP field. The frequency will then similarly return to the original nominal
frequency. The following equations control the spread-spectrum operation:
I wonde if you saw this information.
Unfortunately I could not find any example of it.
Maybe the SDK might be a good base to work.
Best Regards,
Alejandro
