How to enable GPT1 clocks in the device tree on an i.MX8XQuadPlus

[nlbutts]

I would like to use GPT1 (zero offset) on the i.MX8xQuadPlus processor. My device tree is shown below:

/ {
	frequency: frequency {
		compatible = "fsl,imx8qd-freq-gpt";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_frequency>;
		dig-gpio = <&lsio_gpio0 22 GPIO_ACTIVE_HIGH>;
		// GPT0
		reg = <0x0 0x5d150000 0x0 0x4000>;
		clocks = <&clk IMX_SC_R_GPT_2>,
                 <&clk IMX_SC_R_GPT_2>;
		clock-names = "ipg", "per";
		power-domains = <&pd IMX_SC_R_GPT_1>;
	};
};

I have a custom driver that maps the GPT1 address space into the driver and tries to get the clocks. But the clocks always fail.

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->gpt_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(data->gpt_base)) {
		dev_err(dev,"Unable to get gpt base\n");
		return PTR_ERR(data->gpt_base);
	}

	pr_info("Got iomap: 0x%x", data->gpt_base);

	data->gpt_clk_ipg = devm_clk_get(dev, "ipg");
	if (IS_ERR(data->gpt_clk_ipg)) {
		dev_err(dev,"Unable to get ipg clock\n");
		return PTR_ERR(data->gpt_clk_ipg);
	}

	pr_info("Got ipg clock");

	data->gpt_clk_per = devm_clk_get(dev, "per");
	if (IS_ERR(data->gpt_clk_per)) {
		dev_err(dev,"Unable to get per clock\n");
		return PTR_ERR(data->gpt_clk_per);
	}

	pr_info("Got per clock");

	ret = clk_prepare_enable(data->gpt_clk_ipg);
	if (ret) {
		dev_err(dev,"Unable to enable ipg clock\n");
		return ret;
	}

	ret = clk_prepare_enable(data->gpt_clk_per);
	if (ret) {
		dev_err(dev,"Unable to enable per clock\n");
		return ret;
	}

	dev_dbg(dev,"clk : ipg %lu, per %lu\n",
			clk_get_rate(data->gpt_clk_ipg),
			clk_get_rate(data->gpt_clk_per)
			);

I don't think I have the clocks setup correctly in the device tree. If I ignore the clocks I get a kernel panic as the address space doesn't appear to be accessible. 

[igorpadykov]

Hi Nicholas

power and clock are provided for GPT in ATF

https://source.codeaurora.org/external/imx/imx-atf/tree/plat/imx/imx8qm?h=lf-5.4.y

Best regards
igor

[nlbutts]

That appears to be the code for the i.MX8QuadMax not the i.MX8XQuadPlus.

[nlbutts · Accepted solution]

For my future self, you need to declare the gpt1_lpcg devtree node. Which doesn't exist in the i.MX device tree for the 5.4 kernel release.

#include "common.dtsi"

&iomuxc {
	pinctrl_frequency: frequency0grp {
		fsl,pins = <
            IMX8QXP_UART1_RX_LSIO_GPT1_CLK			0x00000060 // IMX8_FREQ_IN
		>;
	};
};

&lsio_subsys {
	gpt1_lpcg: clock-controller@5d550000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5d550000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_GPT_1 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_GPT_1 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_GPT_1 IMX_SC_PM_CLK_PER>,
			 <&lsio_bus_clk>,
			 <&clk IMX_SC_R_GPT_1 IMX_SC_PM_CLK_PER>;
		bit-offset = <0 4 16 20 24>;
		clock-output-names = "gpt2_lpcg_ipg_clk",
				     "gpt2_lpcg_ipg_hf_clk",
				     "gpt2_lpcg_ipg_s_clk",
				     "gpt2_lpcg_ipg_slv_clk",
				     "gpt2_lpcg_ipg_mstr_clk";
		power-domains = <&pd IMX_SC_R_GPT_1>;
	};
};


/ {
	frequency: frequency {
		compatible = "fsl,imx8qd-freq-gpt";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_frequency>;
		dig-gpio = <&lsio_gpio0 22 GPIO_ACTIVE_HIGH>;
		// GPT0
		reg = <0x0 0x5d150000 0x0 0x4000>;
		clocks = <&gpt1_lpcg 0>,
                 <&gpt1_lpcg 4>;
		clock-names = "ipg", "per";
		power-domains = <&pd IMX_SC_R_GPT_1>;
	};
};

This enables the clock and allows me to write a driver for the GPT1 hardware.