How to configure ssi1_clk and clko_clk when used as i2s master sclk and mclk?

[fdact]

Dear Sir or Madam,

                The default code I find ssi1_clk parent is pll3_pfd_508M and clko_clk parent is pll2_528_bus_main_clk that kernel version is 3.0.35.  In order to meet the requirements of master I2S , do I need to modify the clock parent?

                 I don't really understand the difference between the clock, such pll3_pfd_508M and pll2_528_bus_main_clk. Apart from the frequency and frequency of different multiples, what is the difference?

                 Now I set the parent clk for ssi1_clk and clko_clk to pll4, but I find I can't modify clko_clk and ssi1_clk less than 24mhz no matter how to change pll4 clock. 

                  Do you have any known ways to achieve this?

Thanks.

[igorpadykov]

Hi ferdinand

for ssi clock gneration one can look at attached document

Chapter 32 Configuring the SSI Driver.

Typical ssi clock values are given in Table 61-7. SSI Bit Clock and Frame Rate

i.MX6DQ RM http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards

igor

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[fdact]

Hi,

   Thanks for your reply .

    I have to configure the table according to this form. My problem is I can't modify ssi clock value less than 24MHZ, That form we can see the ssi clock can set 11.2896MHZ. So I try to modify ssi1_clk parent clk but also can't work.

Thanks.

[igorpadykov]

Table 61-7 shows typical values used with this processor,

and seems not all values can be obtained with default configuration.

[fdact]

Hi,

    "seems not all values can be obtained with default configuration" 。 But any value in a table can't be achieved. I already said clk can't less than 24MHZ, than means is no matter how calculate the pll and ssi clock the ssi clk always is 24MHZ.

Thanks.