How to change the ddr clock for i.mx6dl-sdp?

[cody]

1.Can we  just change the the ddr  clock in  uboot or the  ddr   driver  which   in the  kernel ？

2.If  we just change  the ddr  clock in  uboot ,will  the  ddr   driver  which   in the  kernel   change the the ddr  clock?

3.How to change the ddr  clock ?

4.And  I  have  change  the ddr  clock in  uboot,the as follows is the log ,is  it  right?

U-Boot 2009.08 ( 3鏈14 2014 - 05:56:35)

CPU: Freescale i.MX6 family TO1.1 at 792 MHz

Thermal sensor with ratio = 188

Temperature:   32 C, calibration data 0x5a500000

mx6q pll1: 792MHz

mx6q pll2: 528MHz

mx6q pll3: 480MHz

mx6q pll8: 50MHz

ipg clock     : 27666666Hz

ipg per clock : 27666666Hz

uart clock    : 80000000Hz

cspi clock    : 60000000Hz

ahb clock     : 55333333Hz

axi clock   : 83000000Hz

emi_slow clock: 41500000Hz

ddr clock     : 166000000Hz

usdhc1 clock  : 83000000Hz

usdhc2 clock  : 83000000Hz

usdhc3 clock  : 83000000Hz

usdhc4 clock  : 83000000Hz

nfc clock     : 24000000Hz

[AnsonHuang · Accepted solution]

Hi, cody

     Our uboot's ddr clock is different from yours, see below, I wonder which uboot release you use, and did you do any changes? And to answer your question as below:

     1. No, you can NOT change ddr clock directly in uboot, and there is no ddr driver in kernel, as ddr clock change need special flow, when uboot or kernel is running on ddr, its freq can NOT be changed. But we have busfreq driver which can change ddr clock automatically if there is no high speed devices active, you can check the busfreq DOC for detail.

     2. No, you can NOT change ddr clock in uboot, we do NOT support that;

     3. Please refer the busfreq driver and DOC;

     4. Your uboot's ddr clock is wrong.

U-Boot 2009.08-00691-g117c045 (Jul 26 2013 - 09:02:56)

CPU: Freescale i.MX6 family TO1.1 at 792 MHz

Thermal sensor with ratio = 184

Temperature:   36 C, calibration data 0x58c50c69

mx6q pll1: 792MHz

mx6q pll2: 528MHz

mx6q pll3: 480MHz

mx6q pll8: 50MHz

ipg clock     : 66000000Hz

ipg per clock : 66000000Hz

uart clock    : 80000000Hz

cspi clock    : 60000000Hz

ahb clock     : 132000000Hz

axi clock   : 198000000Hz

emi_slow clock: 99000000Hz

ddr clock     : 396000000Hz

usdhc1 clock  : 198000000Hz

usdhc2 clock  : 198000000Hz

usdhc3 clock  : 198000000Hz

usdhc4 clock  : 198000000Hz

nfc clock     : 24000000Hz

[cody]

Dear  Yong:

       Thank you very much for your  kindly reply!

1.our   original   log    "ddr clock  396000000Hz " is  the  same  with  yours.

after  change the  code    in  uboot   from   "

#define PLL2_PFD2_FREQ

396000000"          to     #define PLL2_PFD2_FREQ 166000000//396000000

the   ddr clock   change  to   "ddr clock     : 166000000Hz".

as   you  have  said  that   "ou can NOT change ddr clock directly in uboot"   , 

So  the  way  to change  the   ddr  clock   is  not  the  right  way???

2.  Can   you  tell   me  where  to  find   the  busfreq DOC ?

Thanks  .

[AnsonHuang]

You can get our formal release package, there should be linux reference manual for it.

And you can NOT change any clock in uboot, actually, we do NOT support clk change in uboot, not just for ddr, but all clocks.