How to change DDR3 clock speed in U-boot/U-boot SPL?

[amr]

Hello,

I'm working with a custom board based on the MCIMX6UL-EVK (14x14 evk), using the iMX6UL (MCIMX6G3CVM05AB) and the same RAM chip (MT41K256M16LY-093). I've run the NXP DDR Stress Test tool on the board using the default MX6UL DDR3 script, setting MR1 to 0x0004 and the DDR freq to 400MHz, but the calibration fails. I then tried calibrating at 300MHz (see calibration result in this post), and was able to run the stress test overnight. 

I've been trying to compile mainline U-boot using the mx6ul_14x14_evk_defconfig. However, I need to be able to reduce the DDR clock from the default 400Mhz down to 300MHz. Where can this be done?

Thanks

[igorpadykov]

Hi Amr

thanks for sharing solution, in general recommended to change ddr clocks running

code from ocram, during boot it also can be done in plugin:

plugin.S\mx6ul_14x14_evk\freescale\board - uboot-imx - i.MX U-Boot 

Best regards
igor
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[amr]

Thanks for the information - my solution changes the DDR clock in the SPL, which runs from the OCRAM.

[amr]

Managed to do it by adding the following code in board_init_f:

/* Set the DDR clock to 297MHz as follows:
1 - Change PFD0 divider to generate 297MHz
2 - Change pre_periph2_clk_sel to source its clock from PFD0 (by default it takes it from PFD2)
See IMX6ULRM section 18.3
*/

u32 reg;

// Change PFD0 divider to 32
 reg = readl(&mxc_ccm->analog_pfd_528);
 reg &= ~0x3F;
 reg |= 32U;
 writel(reg, &mxc_ccm->analog_pfd_528);
// Toggle PFD0 clock gate
 writel(1U << 7, &mxc_ccm->analog_pfd_528_tog);
 writel(1U << 7, &mxc_ccm->analog_pfd_528_tog);

// Set PRE_PERIPH2_CLK source to PFD0
 reg = readl(&mxc_ccm->cbcmr);
 reg &= ~(3U << 21);
 reg |= (2U << 21);
 writel(reg, &mxc_ccm->cbcmr);

// Enable CLKO1 and CLKO2
 // CLKO1 -> axi_clk_roo
 // CLKO2 -> mmdc_clk_root
 writel(0x05 | (7U << 4) | (1U << 7) |
 (1U << 16) | (7U << 21) | (1U << 24), &mxc_ccm->ccosr);

iomux_v3_cfg_t const clkout_pads[] = {
 MX6_PAD_JTAG_TMS__CCM_CLKO1 | MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
 MX6_PAD_JTAG_TDO__CCM_CLKO2 | MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
 };

imx_iomux_v3_setup_multiple_pads(clkout_pads, ARRAY_SIZE(clkout_pads));