How to change DDR Clock on i.MX7

[davidgeorge]

Does anyone know how to reduce the DDR Clock Rate from 533 MHz on the i.MX7?

Can't see anything about it in the MX7 Reference Manual as yet...

I see the DDR_PLL is set to 1066 MHz - can this we changed?

NXP's DDR Test Tool manages to test at different frequencies - how does it achieve this?

Thanks in advance.

[davidgeorge]

Thanks Igor, that helps.

BTW in iMX7 RM Page 450 onwards covers the PFD Clocks and their frequencies.

[skrap]

Were you successful in doing this?  I am trying a similar experiment, but something's not right.   My changes were:

After boot but before DDRC setup:

1) mux DRAM_ALT_CLK_ROOT to SYS_PLL_PFD0

  (write 0x15000000 to 0x3038a080)

2) mux DRAM_CLK_ROOT to DRAM_ALT_CLK_ROOT

  (write 0x11000000 to 0x30389880)

Then, I proceed with DDRC initialization as normal.  Typically this results in a hang somewhere either in the above or in DDRC initialization.  I'm using GPIO/LED to debug (board doesn't have jtag) so I may be affecting timing by adding those statements.

I'll admit that DDR configuration is definitely not my area of expertise, so there's probably something in there I'm missing.  Do I need to wait for the PLL/PFD to stabilize somehow?  Or are there clock gates I need to flip?  I'm not touching DRAM_PHYM_ALT_CLK_ROOT, which will still be on the 1066 MHz DDR PLL, but that seems ok per the RM.

Any assistance would be much appreciated!

[davidgeorge]

I see I can use the CCM_TARGET_ROOTn registers to select alternative sources for the DRAM_CLK_ROOT and DRAM_PHYM_CLK_ROOT. I can then select clock sources for DRAM_ALT_CLK_ROOT etc..

So I think I will use a PDFn as my DRAM clock source so I can set my required DDR frequency.

But the Reference Manual seems to have no information on the SYS_PLL PDFn clocks.

- how do you set the PDFn frequency?

Reference Manual just says :

PLLs and PFDs: These modules generates the clocks with various frequencies required by different functional blocks. See the PLL and PFD section in Clock Controller Module (CCM)) for information on the PLL and PFD architecture, functional description and programming model.

But there is no PFD section I can see...

Anyone have info on the PDFn clocks?

[Rgulde]

The git link is no longer good. Please update. Need to fix EIM frequency to different value - looking into modifying source PLL frequencies that feed into it's CCGR22 (i.MX7 Solo) .

Reference input clock for any of the PLLs could be selected individually by the
BYPASS_CLK_SRC feed of the PLL control register. Each PLL can use one of the
following clock source as its reference clock:
• 24MHz clock from XTAL.
• External reference clock from CLK1P/N.
• External reference clock from CLK2.

Considering taking the USB_PLL and feeding it to the EIM after it is modified - but as indicated above need to find reference documentation to perform the modification. We don't use USB, but so that PLL is the target for customization to drive the EIM module.

From the table this agrees.
0xA980 EIM_CLK_ROOT 135
000 - OSC_24M
001 - SYS_PLL_PFD2_DIV2
010 - SYS_PLL_DIV4
011 - DDR_PLL_DIV2
100 - SYS_PLL_PFD2
101 - SYS_PLL_PFD3
110 - ENET_PLL_DIV8
111 - USB_PLL

[igorpadykov · Accepted solution]

Hi David

for frequency change example one can look at Chapter 23
CPU Frequency Scaling (CPUFREQ) Driver attached Linux Manual

and sources in ddr3_freq_imx7d.S

linux-2.6-imx.git - Freescale i.MX Linux Tree 

For documentation issues may be suggested to create new thread.

Best regards
igor
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