How long time is needed to load i.MX6SDL eCSPI data shift register from/to FIFO.

[satoshishimoda]

Hi community,

I want to confirm about i.MX6SDL eCSPI behavior.

Please see the attached image, it shows Figure 21-8 in IMX6SDLRM (Rev.1).

I want to confirm about the "waiting" to start next burst transfer (the part of red arrow).

I believe, the term of "waiting" depends on SMC and XCH setting if eCSPI is master mode, right?

On the other hand, if eCSPI is slave mode, i.MX6SDL cannot control the timing when next burst starts.

So would you let me know how fast i.MX6SDL can load the TXDATA from FIFO to shift register (or load the RXDATA from shift register to FIFO) when SS_CTL=0?

And if there is a restriction about this burst transfer in slave mode, please tell me it.

(e.g. This transfer is only for master mode, SS should be negated after each burst in slave mode)

Best Regards,

Satoshi Shimoda

[Yuri · Accepted solution]

  The figure 21-8 relates to the master mode. The opposite device,

in slave mode, is waiting clocks and data from the master. 

The load timing from / to the FIFO to / from shift register is unpredictable.

It would be better to say - the load timing from FIFO to shift register is

application dependent.

Have a great day,
Yuri

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