How enable cache on PCIe in i.MX6?

[massohy]

Dear All,

I am using i.MX6 as PCIe RC. I will write data via PCIe to EP device by ARM CPU.

I want to write with as much as possible large TLP packet by ARM CPU in i.MX6, but I can only 8 byte with memcpy() in yocto linux.

I referred the community, I found that i.MX6 can write by 32 byte unit at PCIe cached.

I referred to patch code attached to https://community.nxp.com/docs/DOC-95014.

I thought it will be ok that I modify pci-imx6.c , but this patch had many different from my driver. And, I thought many codes of modification of its patch was for EP side.  

Please tell me, how can I enable cache on PCIe? If cache is enable, then can I write over 8 bytes unit TLP packet from ARM CPU in RC side i.MX6?

And, if I use PCIe with cached, is that system able to use stable?

Best Regards,

[igorpadykov]

Hi mas

below link provides solution for improving pcie performance using arm core (with cache enabled) or ipu

dma as masters for RC side. I am afraid there are no other ways to improve it.

i.MX6Q PCIe EP/RC Validation System 

Best regards
igor
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