We have a high-resolution LVDS LCD that needs a pixel clock of 74Mhz. However, I noticed that the LTIB 4.1.0 BSP U-boot appears to only support a pixel rate of 65Mhz. The following line in mx5q_sabresd.c is used to initialize the Frame buffer
ret = ipuv3_fb_init(&PK070HD30, di, IPU_PIX_FMT_RGB24, DI_PCLK_LDB, 65000000);
But in addition to changing the frequency there one must update the PLL settings somewhere I'm guessing. The clock parent needs to run at 7x the pixel clock (528Mhz) if I understand correctly. I tried changing the pll2_pfd_352M divider/multipier in mx6q_sabresd.c, but was not able to generate the desired frequency. What's missing ?
Thanks in advance
Here is some info for others who might be facing the same problem
1. In mx6q_sabresd.c add fb_videomode structure that you used in the Kernels ldb.c. Note: I had to had FB_SYNC_EXT "sync" flag to get an image, even though I do not have it on the Linux side.
2. In the same file, update the following lines
|/* pll2_pfd_352M */|
/* disable */
writel(0x1 << 7, ANATOP_BASE_ADDR + 0x104);
/* divider */
writel(0x3F, ANATOP_BASE_ADDR + 0x108);
writel(0x12, ANATOP_BASE_ADDR + 0x104); //Changed from 0x15 to 0x12 to increase PixClk from 65 to 75Mhz
The last two lines determine the Pixel clock. You can get the values used by the Kernel by printing them out in ldb.c (set_pixel_clk)
3. Update Line below to reflect new configuration
|ret = ipuv3_fb_init(&PK070HD30, di, IPU_PIX_FMT_RGB24,||DI_PCLK_LDB, 74183000);|
With this I'm able to see a BMP image, however the colors are incorrect. Looks like there is no support for 24bit LVDS displays. If anyone knows how to solve that problem I'd appreciate it if you could drop a hint here
I'm suspecting the problem is that the frame buffer is configured for 24 bits format, while uboot only appears to support 16bits causing the incorrect color to be displayed. In the interest of booting speed I would prefer to use a 8bit or 16bit BMP anyway, but I'm not sure how to make that show up properly on a 24bit LCD.
I followed the steps outlined below