How can I set the MPU for the memory area used by rpmsg?

[Takashi_Kashiwagi]

Hi community.

I have using i.MX8MP with yocto kirkstone(5.15.71).

Are the memories used by rpmsg the four listed in the dts file: vdev0vring0, vdev0vring1, vdevbuffer, and rsc_table?

For example, if I refer to https://github.com/nxp-imx/linux-imx/blob/lf-5.15.y/arch/arm64/boot/dts/freescale/imx8mp-evk-rpmsg.d..., is it correct to assume that it will look like the following?

	{   /* DDR[0x4000_0000 - 0x8000_0000]: Memory with Normal type, not shareable, non-cacheable */
		.RBAR = ARM_MPU_RBAR(3, 0x40000000U),
		.RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB),
	},
	{   /* DDR[0x55000000 - 0x5500FFFF]: Memory with Normal type, SHAREABLE, not cacheable */
		.RBAR = ARM_MPU_RBAR(4, 0x55000000),	// vdev0vring0: vdev0vring0@55000000,  vdev0vring1: vdev0vring1@55008000
		.RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_64KB),	// for vring. Determine this by referring to the vring item in the dts file.
	},
	{   /* DDR[0x550FF000 - 0x550FFFFF]: Memory with Normal type, SHAREABLE, not cacheable */
		.RBAR = ARM_MPU_RBAR(5, 0x550ff000),	// rsc_table: rsc_table@550ff000
		.RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_4KB),	// for rsc_table. Determine this by referring to the rsc_table item in the dts file.
	},
	{   /* DDR[0x55400000 - 0x54FFFFFF]: Memory with Normal type, SHAREABLE, not cacheable */
		.RBAR = ARM_MPU_RBAR(6, 0x55400000),	// vdevbuffer: vdevbuffer@55400000
		.RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB),	// for vdevbuffer. Determine this by referring to the vdevbuffer item in the dts file.
	},

Best Regards,

KASHIWAGI Takashi

[Zhiming_Liu]

Hi

Are the memories used by rpmsg the four listed in the dts file: vdev0vring0, vdev0vring1, vdevbuffer, and rsc_table?

-->Yes, the related code are like this:

rsc_table.c

void copyResourceTable(void)
{
    /*
     * Resource table should be copied to VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET.
     * VDEV0_VRING_BASE is temperorily kept for backward compatibility, will be
     * removed in future release
     */
    memcpy((void *)VDEV0_VRING_BASE, &resources, sizeof(resources));
    memcpy((void *)(VDEV0_VRING_BASE + RESOURCE_TABLE_OFFSET), &resources, sizeof(resources));
}

board.c

    /* Region 4 DDR[0x4000_0000 - 0x8000_0000]: Memory with Normal type, not shareable, non-cacheable */
    MPU->RBAR = ARM_MPU_RBAR(4, 0x40000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); 
/*
       Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000](please see the
       imx8mp-evk-rpmsg.dts) totally 16MB is revserved for CM7 core. You can put global or static uninitialized
       variables in NonCacheable section(initialized variables in NonCacheable.init section) to make them uncacheable.
       Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 5 set
       the address space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and data section to
       be cacheable if the program running on DDR. The cacheable area base address should be multiples of its size in
       linker file, they can be modified per your needs.
    */
    /* Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]: Memory with Normal type, not shareable, non-cacheable */
    MPU->RBAR = ARM_MPU_RBAR(5, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

Best Regards
Zhiming

[Takashi_Kashiwagi]

Hi @Zhiming_Liu  san

Thank you for reply!

Are the memories used by rpmsg the four listed in the dts file: vdev0vring0, vdev0vring1, vdevbuffer, and rsc_table?
-->Yes, the related code are like this:

Understood. However, this setting allows full access to 0x40000000-0x7FFFFFFF, which is a bit dangerous. It would be easier to understand if the settings for the memory range used by rpmsg were explained in the comments.

Also, in sample board.c, Shared Disable is set. The vring, vdevbuffer, and rsc_table areas used by rpmsg are accessed by both the RTOS and Linux. Is it okay not to set the shared bit?

Best Regards,

KASHIWAGI Takashi

[Zhiming_Liu · Accepted solution]

Hi

The memory can of course be set with more detailed rules.

For the shared bit in board.c, if we check the function in CMSIS\Core\Include\mpu_armv7.h, the IsShareable  is used to control shareable property between multiple bus masters, not two cores.

/**
* MPU Region Attribute and Size Register Value
* 
* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable       Region is shareable between multiple bus masters.
* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable  Sub-region disable field.
* \param Size              Region size of the region to be configured, for example 4K, 8K.
*/                         
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)

Best Regards
Zhiming

[Takashi_Kashiwagi]

Hi @Zhiming_Liu san

Thank you for reply!

For the shared bit in board.c, if we check the function in CMSIS\Core\Include\mpu_armv7.h, the IsShareable is used to control shareable property between multiple bus masters, not two cores.

I understand! My question has been resolved. Thank you.

Best Regards,
KASHIWAGI Takashi