Hardware ECC Accelerator Layout Select Register

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Hardware ECC Accelerator Layout Select Register

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takashitakahash
Contributor III

Hi community.

IMX6DQ RM of sect 17.6.7 Hardware ECC Accelerator Layout Select Register

of  (BCH_LAYOUTSELECT),

Desclibed in Chip Select of CS15 ~ CS0 , as the ball function of iMX6, it is only NAND_CE3 ~ CE0.

What is  CS15 ~ 0 ?

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Yuri
NXP TechSupport
NXP TechSupport

  Only CS0-CS3 bit fields of  BCH_LAYOUTSELECT should be used for i.MX6
 
Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport

  Only CS0-CS3 bit fields of  BCH_LAYOUTSELECT should be used for i.MX6
 
Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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