Getting Understanding of clocks configuration at uboot level

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Getting Understanding of clocks configuration at uboot level

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sd05
Contributor III

Hello Community

I am porting an LCD driver at uboot level for DART-MX8M-Mini based custom board, I have successfully added the driver but somehow display is not getting up and when we analyzed the same from the oscilloscope we are not getting proper clocks, so for this I have to do some hack to enable the MIPI and lcdif clocks. Please share your knowledge and experience how I can enable the clocks. How the clock controller module is configured at uboot level.

Find logs in the attachment

 

and also what are these struct and significance of each field(pdiv,mdiv,sdiv,kdiv)

enum imx_pll14xx_type {
PLL_1416X,
PLL_1443X,
};

/* NOTE: Rate table should be kept sorted in descending order. */
struct imx_pll14xx_rate_table {
unsigned int rate;
unsigned int pdiv;
unsigned int mdiv;
unsigned int sdiv;
unsigned int kdiv;
};

struct imx_pll14xx_clk {
enum imx_pll14xx_type type;
const struct imx_pll14xx_rate_table *rate_table;
int rate_count;
int flags;
};

Thanks in advance!

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igorpadykov
NXP Employee
NXP Employee

Hi Sunidhi

 

unfortunately description of PLL_1416X, PLL_1443X, fields pdiv,mdiv,sdiv,kdiv is not available for

customers as it concerns internal design info, sorry. For understanding of clocks configuration

one can look at

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Setting-i-MX8M-Mini-and-Nano-MIPI-DPHY-C...

one can check #define PLLCTRL_SET_PMS(x) in linux and uboot drivers:

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_4....

https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/video/imx/sec_mipi_dsim.c?h=imx_v2...

 

Best regards
igor

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