For the Power-up sequence of MX6DL SABRE-SDP.

[yuuki]

In the SABRE-SDP, MMPF0100F0 and i.MX6DL are used.

The output of SW1AB of MMPF0100F0 is connected to VDDARM of i.MX6DL.
And the output of SW1C of MMPF0100F0 is connected to VDDSCC of i.MX6DL.

According to description of 6.1.1Device Start-up Configuration ("F0") in MMPF0100 datasheet(Rev7),
- SW1C is outputted after a SW1AB output.
- This interval is 2.0 ms.

However, the following is explained by the datasheet of MCIMX6.
"— VDD_ARM_IN and VDD_SOC_IN may be supplied from the same source, or
  — VDD_SOC_IN can be supplied before VDD_ARM_IN with a maximum delay of 1 ms."

I think the Power-up sequence of MMPF0100F0 does not match i.MX6.

Does it have any problems?
Does it have any bad effects on i.MX6?

Best Regards,

[Yuri · Accepted solution]

    You are right, some power up sequence violation takes place for the mentioned configuration,

  when the external SRC_POR_B signal is not used. So, one of solutions is applying external
POR : in such case “VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no
restrictions”, assuming the external POR “remains low (asserted) until the VDD_ARM_CAP and
VDD_SOC_CAP supplies are stable”.

Have a great day,
Yuri

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