sabreSD sleep power consumption, wake-up time

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sabreSD sleep power consumption, wake-up time

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joštnovak
Contributor II

Hi,

we are trying to measure power requirements for i.MX6Q system

on SabreSD (Quad).

When going to lowest possible power saving mode with Linux

command:


echo mem > /sys/power/state

The whole board is still consuming 0,96W (at 5V input). We have

disconnected and disabled all peripherals.

We would expect somewhere around 50 mW based on

infomation in your i.MX6 application notes.

Why can we achieve lower value than 1W? This is too much.

The second problm is it takes around 300 ms to wake up. i.MX6

RM says 10ms.

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AnsonHuang
NXP Employee
NXP Employee

Hi, Novak

     You can refer to our power application note http://cache.freescale.com/files/32bit/doc/app_note/AN4509.pdf?fsrch=1&WT_TYPE=Application%20Notes&W...

     Our DSM power number of SOC level is less than 30mW including DDR3 chip. For the SabreSD board, as there is many power rails that can NOT be shut down, so if we want to do the board level power consumption optimization, many board level hardware rework need to do, we ever done some experiment, and the board level power can be lower to ~10.85mA@3.74V, but only RTC wake up is available, as all wake up source's power is off, below is the experiment we did, hope it is helpful for you.

     And for the wake up time, many common linux driver has latency, this is kernel issue. Basic resume flow is: wakeup source interrupt pending-> SOC wake up-> ARM core contest restore->linux driver resume, the main latency is caused by linux driver. You can remove as much drivers as possible, then redo the time measurement. If I remembered correct, the USB and MMC driver both take more than 150ms to resume, please remove them and have a try.

SYS_4V2 SYS_4V2 battery cable 120mA@3.3V (no bypass)
112.6mA@3.3V (bypass battery and max8903,power supply to SYS_4V2 directly)
56.6mA@3.3V (bypass battery and max8903,power supply to SYS_4V2 directly, config SW1A&B and SW2 PFM then enter into resume)
5/22:75.8mA@3.3V ( if D10 instead of 0.02ohm, and config all switch standbymode PFM)
5/24:51.2mA@3.3V on board(config all switch standbymode PFM)
5/25:49.2mA@3.3V on board(config SW4LX  off in standby mode, config other switchs PFM in standby mode, config VGEN1 and VGEN2 off in standby mode)
5/28:24.4mA@3.3V on board(config SW2LX and SW4LX  off in standby mode, config other switchs PFM in standby mode, config VGEN1 and VGEN2 off in standby mode,DFS rootfs)
5/29~5/30:17.8mA@3.3V on board ,19.2mA@3.0V on board ,17.2mA@4.0V on board (config SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode, config other switchs PFM in standby mode, config VGEN1,VGEN2,VGEN3 and VGEN4 off in standby mode, disable eth phy by removing probe code in fec.c,then close VGEN6,SD rootfs )
5/30PM:16.25mA@3.77V on board (no bypass,short cable connected with battery ,config SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode, config other switchs PFM in standby mode, config VGEN1,VGEN2,VGEN3 and VGEN4 off in standby mode, disable eth phy by removing probe code in fec.c,then close VGEN6,SD rootfs )
5/31AM:14.2mA@3.77V on board ,15.2mA@3.0V on board ,13.7mA@4.0V on board (config SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode, config other switchs PFM in standby mode, config VGEN1,VGEN2,VGEN3 and VGEN4 off in standby mode, disable eth phy by removing probe code in fec.c,then close VGEN6,Remove LED D2,SD rootfs )
5/31AM:13.65mA@3.75V on board (no bypass,short cable connected with battery ,config SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode, config other switchs PFM in standby mode, config VGEN1,VGEN2,VGEN3 and VGEN4 off in standby mode, disable eth phy by removing probe code in fec.c,then close VGEN6,,Remove LED D2,SD rootfs )
5/31PM: 10.85mA@3.74V on board (no bypass,short cable connected with battery ,config SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode, config other switchs PFM in standby mode, config VGEN1,VGEN2,VGEN3 and VGEN4 off in standby mode, disable eth phy by removing probe code in fec.c,then close VGEN6,,Remove LED D2,Remove LED D1,SD rootfs )

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dehakuran
Contributor I

Hi Huang,

I don't know if this thread is still active but I believe it is the right place to ask.

I have a custom board with WEC7 running, where I don't have a pmic but I can power-down peripherals by gpios. Also I have implemented analog circuit to regulate voltage from 1.2V to 0.9V when Pmic_stanby_req is asserted (3.3V and 1.5V is not changed). So far it seems to be working however even if I have suspend to RAM, My consumption is around 190 mW,

I have disconnected all the peripherals so I know that consumption is somewhere on the soc. I was wondering what could I have missed, so may be if you can tell what have you done step by step, I could clarify my problem.

For instance

"SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode" means -> PMIC does ???

I was wondering if anyone can enlighten me about following questions

1- How much work is done automaticly when we set CCM->LPGCR Stop mode bits,

- Clocks disabled

- ?

2- If we shut-down analog domain via clearing PMU_MISC0->STOP_MODE_CONFIG, should we also explicitly power down all PLL's?

3- If PLL's are power down, should we also explicitly disable PHY's?

Cheers,

DK

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AnsonHuang
NXP Employee
NXP Employee

For instance

"SW2LX and SW4LX and SW1ALX&SW1BLX off in standby mode" means -> PMIC does ???

[Anson] PMIC set this power rail to be auto disabled in standby mode.

I was wondering if anyone can enlighten me about following questions

1- How much work is done automaticly when we set CCM->LPGCR Stop mode bits,

- Clocks disabled

- ?

[Anson] 1. clock disabled; 2. All PLLs/PFDs off; 3. 24MHz XTAL off; 4. ANATOP run into stop mode, internal LDOs will be bypassed; 5. PMIC_VSTBY_REQ is asserted so that external power rails can be off or set to low voltage.

2- If we shut-down analog domain via clearing PMU_MISC0->STOP_MODE_CONFIG, should we also explicitly power down all PLL's?

[Anson] STOP_MODE _CONFIG is clear by default, if setting it, then some of the anatop modules are on during STOP mode, see the RM PMU chapter of register description  for details. you can clear STOp_MODE_CONFIG to see how low power you can get.

3- If PLL's are power down, should we also explicitly disable PHY's?

[Anson] Yes, modules driver need to disable its PHYs, such as USB, PCIe etc.

I think you should measure all possible power rails consumption, then we will know what modules are still active during STOP mode, such as we need to know how much VDDSOC consumes, VDDHIGH etc.

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dehakuran
Contributor I

Yongcai Huang wrote:

3- If PLL's are power down, should we also explicitly disable PHY's?

[Anson] Yes, modules driver need to disable its PHYs, such as USB, PCIe etc.

[DK] Even if I power down PHY's explicity, I don't see any progress on consumption. I checked my implementation with Linux BSP and it looks identical. Do I need to change voltage on supplies also?( i.e. : SATA_VP, SATA_VPH, etc.)

I think you should measure all possible power rails consumption, then we will know what modules are still active during STOP mode, such as we need to know how much VDDSOC consumes, VDDHIGH etc.

[DK] This is what I am planning to do so

One more question about DDR's in dormant mode:

Is this how the procedure goes in Linux BSP for SDB?

1- Software disables auto-savings for MMDC

2- Software puts MMDC into self-refresh

3- MMDC starts polling for DFVS

4- PMIC lowers voltages

5- MMDC reduces DDR's frequency

6- Goes to Low power mode??

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AnsonHuang
NXP Employee
NXP Employee

DDR in dormant mode only does below actions:

before enter dormant mode:

1. disable auto self-refresh;

2. force DDR into self-refresh;

3. save DDR/IO config;

4. put DDR/IO into low power mode;

after exit from dormant mode:

1.restore DDR/IO config;

2.force DDR out of self-refresh, known as DVFS mode of MMDC;

3. enable auto self-refresh mode.

We are not touching the DDR clock, you can read the dormant mode code suspend-imx6.S.

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dehakuran
Contributor I

Hi,

In suspend-imx6.s

Line 1129

poll_dvfs_set_1:
ldr r0, [r1, #0x404]
and r0, r0, #0x2000000
cmp r0, #0x2000000
bne poll_dvfs_set_1

It seems like we are touching clock, or voltage, otherwise why there is a dvfs loop before going to sleep??

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AnsonHuang
NXP Employee
NXP Employee

This is to put MMDC into self-refresh mode, it is called dvfs in MMDC module.

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