Flex_ SPI Interface Access FPGA Timing Problem

[jiaxin]

Hi,sir

I am using Flex from i.MX RT1052.  When accessing FPGA through the Flex_ SPI(4-wire) interface, the write data sent by ARM is shown in the following figure. How can I cancel the idle (without clock) section in the middle? Or how to make this idle period a fixed length?

Similarly, when I use IMX. 8, I use Flex_ When Flex_SPI reads and writes to access FPGA, the clock emitted is continuous, and the clock length is consistent with the configured length. These two chips are in Flex_SPI Do I need to pay attention to any differences when using SPI?

[jingpan]

Hi @jiaxin ,

Can you share a demo project?

Regards,

Jing

[jiaxin]

Hi.jingpan

Sorry, since it is not an ARM program written by me, there is no demo program to provide for the time being. Because the Flex SPI is connected to the FPGA, and the read command sent to FPGA side is 0xEC, the write command is 0x32, and the data is followed; I would like to know what could cause this timing?

[jingpan]

Hi @jiaxin ,

Sorry but I can't get enough information from your picture. How is the way you read FPGA, how do you set the cache and flexspi buffer?

Regards,

Jing