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FEC Settings

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lifusong
Contributor IV

Below code.  what's means for that RED MARK Character ? How to Set this by the HW designed? and what is it have function?

enet {

pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
>;
};

pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
>;
};

pinctrl_enet_3: enetgrp-3 {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
>;
};

pinctrl_enet_irq: enetirqgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__ENET_IRQ      0x000b1
>;
};
};
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gusarambula
NXP TechSupport
NXP TechSupport

The MX6QDL_PAD_GPIO_16__ENET_REF_CLK refers to the ENET_REF_CLK function trough the GPIO16 pin. This function varies between the different Ethernet modes. In the case of the SABRE board where RGMII is used, this function is used as an input for the 125 MHz clock.

The PAD control for this pin is located on Register IOMUXC_SW_PAD_CTL_PAD_GPIO16. Details on this register can be found on section 36.4.386 of the i.MX6D/Q Reference Manual.

As for the way the device tree pin control works, you may find more details on the following document:

Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

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