External clock that provide root clock for SAI3 and SPDIF modules freeze the system

[Aurelien_BOUIN]

Hi,
I am trying to use an external clock of 22579200 Hz on CLK_EXT3 Ball AG11 of an iMX8MM
This clock is supposed to provide the clock to SAI3 and SPDIF modules
Unfortunately the board freeze once it try to change the clock parent
This is pretty close to the thread : https://community.nxp.com/thread/496566

Here is my relevant dts declarations :

clocks {
    clk_ext3: clock@4 {
        compatible = "fixed-clock";
        reg = <5>;
        #clock-cells = <0>;
        clock-frequency = <22579200>;
        clock-output-names = "clk_ext3";
    };
};

    captina: captina {
        compatible = "cp,captina";
        #sound-dai-cells = <0>;/* simple-card needs */
        clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
        clock-names = "mclk";
    };

    sound-captina {
        compatible = "simple-audio-card";
        simple-audio-card,name = "captina Card";
        simple-audio-card,format = "i2s";
        simple-audio-card,bitclock-master = <&dailink0_master>;
        simple-audio-card,frame-master = <&dailink0_master>;
        /* Switch between Right and Left channels */
        simple-audio-card,frame-inversion;
        simple-audio-card,widgets =
            "Line", "Line Out Jack",
            "Line", "Line In Jack";
        simple-audio-card,routing =
            "Line Out Jack", "LOUT",
            "Line Out Jack", "ROUT",
            "LIN", "Line In Jack",
            "RIN", "Line In Jack";
        dailink0_master: simple-audio-card,cpu {
            sound-dai = <&sai3>;
            dai-tdm-slot-num = <2>;
            dai-tdm-slot-width = <32>;
        };
        simple-audio-card,codec {
            sound-dai = <&captina>;
            clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
            clock-names = "mclk";
        };
    };

    sound-spdif {
        compatible = "fsl,imx-audio-spdif";
        model = "imx-spdif";
        spdif-controller = <&spdif1>;
        spdif-out;
        spdif-in;
    };


pinctrl_sai3: sai3grp {
    fsl,pins = <
        MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
        MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
        MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
         /* RXFS have to be tri state since TXFS also play on the same wire */
        MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x19
        MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
        MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK      0xd6
        /* MCLK input from oscillator */
        MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3   0x00000011
    >;
};

&sai3 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai3>;
    #sound-dai-cells = <0>;/* simple-card needs */
    assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
    assigned-clock-parents = <&clk IMX8MM_CLK_EXT3>;
    assigned-clock-rates = <22579200>;
    status = "okay";
};

&spdif1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_spdif1>;
    assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
    assigned-clock-parents = <&clk IMX8MM_CLK_EXT3>;
    assigned-clock-rates = <22579200>;
    clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
        <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
        <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
        <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
        <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
        <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
    clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
        "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
    status = "okay";
};

when sai3 and spdif have their assigned-clock-parents like this :

assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;

The system doesn't freeze, but they are not sync on clk_ext3

Thank you by advance if you have any reference, any hints, any help, anything

Regards
Aurelien BOUIN

[krekeltronics]

thanks - please share specifically the steps you are using with any logs, source code, etc. so we can be sure to replicate on our end. So far, our experiences do not match. Because you have said that you have been able to clock SPDIF and SAI3 from the same clock without locking up the system, I want to be able to match your experience on our end. Then we can integrate that solution into our system, which requires externally synchronized clocking of both SPDIF and SAI3.

As of this moment, any time we attempt to boot the system with this configuration, we get the hang. Please help me understand what we might be missing.

Cheers,

Patrick

[fabio_estevam · Accepted solution]

Hi Patrick,

I have applied the following patch in order to use CLK_EXT3 as SAI3 source in a i.MX8MM EVK:

http://code.bulix.org/vst00z-1125422 

Kernel booted without any hang.

Please note that I have disabled the camera because on i.MX8MM EVK the GPIO1_IO06 pin is used as camera reset originally. Make sure there is no pin conflit on your dts as well.

Another experiment we did was to boot the kernel without supplying the EXT_CLK3 clock. In this case the kernel hangs and as soon as we turn on the external clock generator, then the boot proceeds.

So we see the same behavior in U-Boot and kernel: the clock switch is successful as long as EXT_CLK3 is present. If it is not present, then the system hangs.

Regards,

Fabio Estevam

[edwardtyrrell]

Hi @fabio_estevam 

The patch link you supplied in this fix no longer works, could you please supply another?

Thanks.

[Aurelien_BOUIN]

Hello Fabio & Igor,

Thank you very much for your time and your support!

This is now working as long as EXT_CLK3 is present and correctly voltage adjusted !

Best regards,

Aurelien BOUIN

[gkilmer]

I believe Aurelien and I have the same boards from a hardware perspective. I have re-attached the text showing my system accepting the register settings in U-Boot but then hanging when I try to finish the boot sequence. This might have been the behavior Aurelien was referring to I'm not sure. See below for the sequence:

emperor=>
emperor=> mw.l 0x30330040 0x6
emperor=> mw.l 0x3038a680 0x06000000
emperor=>
emperor=>
emperor=> boot
switch to partitions #0, OK
mmc2(part 0) is current device
4138 bytes read in 6 ms (672.9 KiB/s)
Running bootscript from mmc ...
## Executing script at 40480000
Jabber like a penguin if you like penguins
Scanning bootloader partitons(mmcblk2p1) for [boot_vars.cfg;partition_vars.cfg].
130 bytes read in 3 ms (42 KiB/s)
Bootloader variable-file imported OK.
80 bytes read in 1 ms (78.1 KiB/s)
Partition variable-file imported OK.
Starting emperor-env.txt
Parameters used :
* image:/boot/Image
* fdt_file:/boot/emperor.dtb
* initrd_file:none
* the_base_cmdline_args:console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200
* mmcdev:2
* mmcpart:4
switch to partitions #0, OK
mmc2(part 0) is current device
25184768 bytes read in 345 ms (69.6 MiB/s)
Booting from mmc ...
Kernel image loaded
37512 bytes read in 6 ms (6 MiB/s)
FDT loaded
Booting without initramfs
## Flattened Device Tree blob at 43000000
Booting using the fdt blob at 0x43000000
Using Device Tree in place at 0000000043000000, end 000000004300c287
Found /vpu_g1@38300000 node
Modify /vpu_g1@38300000:status disabled
Found /vpu_g2@38310000 node
Modify /vpu_g2@38310000:status disabled
Found /vpu_h1@38320000 node
Modify /vpu_h1@38320000:status disabled

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 4.19.35-rt20-rc1-funkadelic (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT RT Tue Jan 21 22:23:55 UTC 2020
[ 0.000000] Machine model: FSL i.MX8MM Emperor board
[ 0.000000] earlycon: ec_imx6q0 at MMIO 0x0000000030890000 (options '115200')

.......

[ 2.859963] sdhci-esdhc-imx 30b40000.mmc: Linked as a consumer to regulator.5
[ 2.902475] mmc0: SDHCI controller on 30b40000.mmc [30b40000.mmc] using ADMA
[ 2.911643] mmc2: CQHCI version 5.10
[ 2.915869] sdhci-esdhc-imx 30b60000.mmc: Linked as a consumer to regulator.5
[ 2.923723] random: fast init done
[ 2.961915] mmc2: SDHCI controller on 30b60000.mmc [30b60000.mmc] using ADMA
[ 2.977774] caam 30900000.caam: ERA source: CCBVID.
[ 2.988820] caam 30900000.caam: device ID = 0x0a16040100000000 (Era 9)
[ 2.995374] caam 30900000.caam: job rings = 3, qi = 0, dpaa2 = no
[ 3.016310] caam algorithms registered in /proc/crypto
[ 3.024946] caam_jr 30901000.jr0: registering rng-caam
[ 3.030427] caam 30900000.caam: caam pkc algorithms registered in /proc/crypto
[ 3.039609] platform caam_sm: blkkey_ex: 2 keystore units available
[ 3.046319] caam 30900000.caam: SM test passed
[ 3.051204] caam-snvs 30370000.caam-snvs: can't get snvs clock
[ 3.057203] caam-snvs 30370000.caam-snvs: violation handlers armed - non-secure state
[ 3.066296] usbcore: registered new interface driver usbhid
[ 3.071886] usbhid: USB HID core driver
[ 3.075924] mmc2: Command Queue Engine enabled
[ 3.079635] optee: probing for conduit method from DT.

[gkilmer]

Fabio,

It takes the commands in U-Boot but then once I try to boot when these registers are set the system hangs. See the attached file showing where our system hangs.

Grant

emperor=>
emperor=> mw.l 0x30330040 0x6
emperor=> mw.l 0x3038a680 0x06000000
emperor=>
emperor=>
emperor=> boot
switch to partitions #0, OK
mmc2(part 0) is current device
4138 bytes read in 6 ms (672.9 KiB/s)
Running bootscript from mmc ...
## Executing script at 40480000
Jabber like a penguin if you like penguins
Scanning bootloader partitons(mmcblk2p1) for [boot_vars.cfg;partition_vars.cfg].
130 bytes read in 3 ms (42 KiB/s)
Bootloader variable-file imported OK.
80 bytes read in 1 ms (78.1 KiB/s)
Partition variable-file imported OK.
Starting emperor-env.txt
Parameters used :
* image:/boot/Image
* fdt_file:/boot/emperor.dtb
* initrd_file:none
* the_base_cmdline_args:console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200
* mmcdev:2
* mmcpart:4
switch to partitions #0, OK
mmc2(part 0) is current device
25184768 bytes read in 345 ms (69.6 MiB/s)
Booting from mmc ...
Kernel image loaded
37512 bytes read in 6 ms (6 MiB/s)
FDT loaded
Booting without initramfs
## Flattened Device Tree blob at 43000000
Booting using the fdt blob at 0x43000000
Using Device Tree in place at 0000000043000000, end 000000004300c287
Found /vpu_g1@38300000 node
Modify /vpu_g1@38300000:status disabled
Found /vpu_g2@38310000 node
Modify /vpu_g2@38310000:status disabled
Found /vpu_h1@38320000 node
Modify /vpu_h1@38320000:status disabled

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 4.19.35-rt20-rc1-funkadelic (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT RT Tue Jan 21 22:23:55 UTC 2020
[ 0.000000] Machine model: FSL i.MX8MM Emperor board
[ 0.000000] earlycon: ec_imx6q0 at MMIO 0x0000000030890000 (options '115200')

.......

[ 2.859963] sdhci-esdhc-imx 30b40000.mmc: Linked as a consumer to regulator.5
[ 2.902475] mmc0: SDHCI controller on 30b40000.mmc [30b40000.mmc] using ADMA
[ 2.911643] mmc2: CQHCI version 5.10
[ 2.915869] sdhci-esdhc-imx 30b60000.mmc: Linked as a consumer to regulator.5
[ 2.923723] random: fast init done
[ 2.961915] mmc2: SDHCI controller on 30b60000.mmc [30b60000.mmc] using ADMA
[ 2.977774] caam 30900000.caam: ERA source: CCBVID.
[ 2.988820] caam 30900000.caam: device ID = 0x0a16040100000000 (Era 9)
[ 2.995374] caam 30900000.caam: job rings = 3, qi = 0, dpaa2 = no
[ 3.016310] caam algorithms registered in /proc/crypto
[ 3.024946] caam_jr 30901000.jr0: registering rng-caam
[ 3.030427] caam 30900000.caam: caam pkc algorithms registered in /proc/crypto
[ 3.039609] platform caam_sm: blkkey_ex: 2 keystore units available
[ 3.046319] caam 30900000.caam: SM test passed
[ 3.051204] caam-snvs 30370000.caam-snvs: can't get snvs clock
[ 3.057203] caam-snvs 30370000.caam-snvs: violation handlers armed - non-secure state
[ 3.066296] usbcore: registered new interface driver usbhid
[ 3.071886] usbhid: USB HID core driver
[ 3.075924] mmc2: Command Queue Engine enabled
[ 3.079635] optee: probing for conduit method from DT.

[fabio_estevam]

Hi Grant,

Do you mean that NVCC_GPIO1 is supplied with 3.3V in your board?

Regards,

Fabio Estevam

[fabio_estevam]

Also, could you please try it from U-Boot so that we don't have SAI3 operational initially?

[igorpadykov]

Hi Aurelien

I will check internally and update.

Best regards
igor

[Aurelien_BOUIN]

Hello Igor,

I received an email from you but it doesn't appear here, so I copy paste your email here and answer after :

I asked internally and got below:

-------------------

Unfortunately, we do not have a board that uses MCLK_EXT3 as clock input to SAI or SPDIF. And apparently, there is nothing wrong with your DTS file - it seems right.

Try to dump the IOMUXC_GPR2 and IOMUXC_GPR7 registers.

Let me know any update.

------------------

Best regards
igor

My answer :

Thank you for your confirmation,

I can't access any register when the system is freeze, so I won't be able to give the internal value of IOMUXC_GPR2 and IOMUXC_GPR7 registers

I am trying to use CLKIN to provide clocks to audio_pll2, unfortunately it doesn't seem to work either

Also I can't get any clock from CLKOUT ball H26 and J26, please take a look at this thread where I have add my comments : https://community.nxp.com/message/1264391?commentID=1264391#comment-1264391

Thank you again for your time and your help

Best Regards,

Aurelien BOUIN

[krekeltronics]

Thank you, Igor. This has become a pressing issue as we're now at risk of schedule delay related to finalizing our new hardware revision. Please keep us posted with details as to whether or not this is indeed a supported configuration, and if so, what adjustments we could make on the software configuration or pin/layout side to accommodate. 

Best regards,

Patrick Krekelberg

[igorpadykov]

I asked internally and got below:

-------------------

Unfortunately, we do not have a board that uses MCLK_EXT3 as clock input to SAI or SPDIF. And apparently, there is nothing wrong with your DTS file - it seems right.

1. Try to dump the IOMUXC_GPR2 and IOMUXC_GPR7 registers.

2. Other hint: it may be necessary to set the SION bit in the below pin. Try to set this way:

MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3   0x40000116

Let me know any update.

------------------

Best regards
igor